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參數(shù)資料
| 型號： | FB2041 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 7-bit Futurebus+ transceiver(7位預置總線收發(fā)器) |
| 中文描述： | 7位Futurebus收發(fā)器（7位預置總線收發(fā)器） |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 148K |
| 代理商： | FB2041 |
Philips Semiconductors
Product specification
FB2041
7-bit Futurebus+ transceiver
1995 May 25
3
PIN CONFIGURATION
52 51 50 49 48 47 46
45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19
20
21 22 23 24 25 26
BUS GND
B1
BUS GND
B2
BUS GND
B3
BUS GND
B4
BUS GND
B5
BUS GND
B6
BUS GND
LOGIC GND
AI1
AI2
AO2
LOGIC GND
AO3
LOGIC GND
AI3
AI4
AO4
LOGIC GND
AO5
LOGIC GND
A
L
A
L
T
T
A
O
B
L
A
A
O
T
T
B
O
B
B
B
L
O
7-Bit Transceiver
FB2041
52-lead PQFP
A
O
O
O
The B-port interfaces to “Backplane Transceiver Logic” (See the
IEEE 1194.1 BTL standard). BTL features low power consumption
by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced
capacitive loading by placing an internal series diode on the drivers.
BTL also provides incident wave switching, a necessity for high
performance backplanes.
There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement. The TTL/BTL output drivers for bit 0 are enabled with
OEA1/OEB1, output drivers for bits 1–2–3 are enabled with
OEA2/OEB2 and output drivers for bits 4–5–6 are enabled with
OEA3/OEB3.
The A-port operates at TTL levels with separate I/O. The 3-state
A-port drivers are enabled when OEAn goes High after an extra 6ns
delay which is built in to provide a break-before-make function.
When OEAn goes Low, A-port drivers become High impedance
without any extra delay. During power on/off cycles, the A-port
drivers are held in a High impedance state when V
CC
is below 2.5V.
The B-port has an output enable, OEB0, which affects all seven
drivers. When OEB0 is High and OEBn is Low the output driver will
be enabled. When OEB0 is Low or if OEBn is High, the B-port
drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off
cycles to insure glitch free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
5V level while V
CC
is Low. If live insertion is not a requirement, the
BIAS V pin should be tied to a V
CC
pin.
The LOGIC GND and BUS GND pins are isolated in the package to
minimize noise coupling between the BTL and TTL sides. These
pins should be tied to a common ground external to the package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble-shoot.
The LOGIC V
CC
and BUS V
CC
pins are also isolated internally to
minimize noise and may be externally decoupled separately or
simply tied together.
JTAG boundary scan functionality is provided as an option with
signals TMS, TCK, TDI and TDO. When this option is not present,
TMS and TCK are no-connects (no bond wires) and TDI and TDO
are shorted together internally.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| FB2041A | 制造商:TI 制造商全稱:Texas Instruments 功能描述:7-BIT TTL/BTL TRANSCEIVER |
| FB2041BB | 制造商:PHILIPS-SEMI 功能描述: |
| FB2041BB-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:7-Bit Bus Transceiver |
| FB-20-5 | 制造商:Polycase 功能描述:Enclosure; Key Fob, ABS Plastic; 2.10 x 1.30 x 0.58 in; Black with Gray Buttons |
| FB20601C | 制造商:Marathon Special Products 功能描述: |
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