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參數(shù)資料
| 型號： | FAN6921MRMY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 1210K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOICN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM） |
| 電流 - 啟動： | 10µA |
| 電源電壓： | 8.5 V ~ 25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
?2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921MR Rev. 1.0.4
17
RANGE Pin
A built-in low voltage MOSFET can be turned on or off
according to V
VIN
voltage level. The drain pin of this
internal MOSFET is connected to the RANGE pin.
Figure 29 shows the status curve of V
VIN
voltage level
and RANGE impedance (open or ground).
Figure 29. Hysteresis Behavior between RANGE Pin
and VIN Pin Voltage
Zero Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when PFC MOS is
off, the stored energy of the PFC inductor starts to
release to the output load. Then the drain voltage of
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin
voltage is lower than the triggering voltage (1.75V
typical), the PFC gate signal is sent again to start a new
switching cycle.
If PFC operation needs to be shut down due to
abnormal condition, it is suggested to pull the ZCD pin
LOW, voltage under 0.2 V (typical), to activate the PFC
disable function to stop PFC switching operation.
For preventing excessive high switching frequency at
light load, a built-in inhibit timer is used to limit the
minimum t
OFF
time. Even if the ZCD signal has been
detected, the PFC gate signal still would not be sent
during the inhibit time (2.5 祍 typical).
Figure 30. Internal Block of the Zero-Current
Detection
Figure 31. Operation Waveforms of PFC Zero-
Current Detection
Protection for PFC Stage
PFC Output Voltage UVP and OVP (INV Pin)
FAN6921MR provides several kinds of protection for
PFC stage. PFC output over- and under-voltage are
essential for PFC stage. Both are detected and
determined by INV pin voltage, as shown in Figure 32.
When INV pin voltage is over 2.75 V or under 0.45 V,
due to overshoot or abnormal conditions and lasts for a
de-bounce time around 70 祍, the OVP or UVP circuit is
activated to stop PFC switching operation immediately.
The INV pin is not only used to receive and regulate
PFC output voltage, but can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
Figure 32. Internal Block of PFC Over-and Under-
Voltage Protection
5
10V
1.75V
ZCD
FAN6921
1:n
V
AC
L
b
1.4V
PFC Gate On
2.1V
R
S
Q
PFC Gate
Drive
R
S
Q
R
ZCD
0.2V
1
V
COMP
Error
Amplifier
COMP
FAN6921
OVP = (V
INV
e 2.75V)
UVP = (V
INV
d 0.45V)
Voltage
Detector
INV
C
O
PFC V
O
Deboun ce
Time
Driver
V
REF
(2.5V)
C
COMP
R
1
R
2
2
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