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參數(shù)資料
| 型號： | FAN5365UC06X |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1.84 A SWITCHING REGULATOR, 6600 kHz SWITCHING FREQ-MAX, PBGA9 |
| 封裝： | 1.27 X 1.29 MM, 0.40 MM PITCH, WLCSP-9 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大小： | 1014K |
| 代理商： | FAN5365UC06X |
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5365 Rev. 1.0.4
18
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Power-Up, EN, and Soft-Start
All internal circuits remain de-biased and the IC is in a very
low quiescent current state until the following are true:
VIN is above its rising UVLO threshold, and
EN is HIGH.
At that point, the IC begins a soft-start cycle, its I
2C interface is
enabled, and its registers are loaded with their default values.
During the initial soft-start, VOUT ramps linearly to the
setpoint programmed in the VSEL register selected by the
VSEL pin. The soft-start features a fixed output voltage slew
rate of 20V/ms and achieves regulation approximately 90
μs
after EN rises. PFM mode is enabled during soft-start until
the output is in regulation, regardless of the MODE bit
settings. This allows the regulator to start into a partially
charged output without discharging it; in other words, the
regulator does not allow current to flow from the load back to
the battery.
As soon as the output has reached its setpoint, the control
forces PWM mode for about 85
μs to allow all internal control
circuits to calibrate.
Table 3. Soft-Start Timing
Symbol
Description
Value (
μs)
tSSDLY
Time from EN to start of soft-
start ramp
25
tREG
VOUT ramp start to regulation
(VSEL–0.1) X 53
tPOK
PWROK (CONTROL2[5])
rising from tREG
11
tCAL
Regulator stays in PWM
mode during this time
10
V
OUT
0
EN
PWROK
t
REG
VSEL
t
POK
t
CA L (FPWM)
t
SSD LY
Figure 35. Soft-Start Timing
Table 4. EN_DCDC Behavior
EN_DCDC Bit
EN Pin
I
2C
REGULATOR
0
OFF
1
ON
1
0
OFF
0
1
ON
OFF
Software Enable
The EN_DCDC bit, VSELx[7], can be used to enable the
regulator in conjunction with the EN pin. Setting EN_DCDC with
EN HIGH begins the soft-start sequence described above.
Light-Load (PFM) Operation
The FAN5365 provides a low ripple, single-pulse, PFM mode
that ensures:
Smooth transitions between PFM and PWM modes
Single-pulse operation for low ripple
Predictable PFM entry and exit currents.
PFM begins after the inductor current has become
discontinuous, crossing zero during the PWM cycle for 32
consecutive cycles. PFM exit occurs when discontinuous
current mode (DCM) operation cannot supply sufficient
current to maintain regulation. During PFM mode, the
inductor current ripple is about 40% higher than in PWM
mode. The load current required to exit PFM mode is
thereby about 20% higher than the load current required to
enter PFM mode, providing sufficient hysteresis to prevent
“mode chatter.”
While PWM ripple voltage is typically less than 4mVP-P, PFM
ripple voltage can be up to 30mVP-P during very light load. To
prevent significant undershoot when a load transient occurs,
the initial DC setpoint for the regulator in PFM mode is set
10mV higher than in PWM mode. This offset decays to about
5mV after the regulator has been in PFM mode for ~100
μs.
The maximum instantaneous voltage in PFM is 30mV above
the setpoint.
PFM mode can be disabled by writing to the mode control
bits: CONTROL1[3:0] (see Table 5)
Output Voltage Transitions
The IC regulates VOUT to one of two setpoint voltages, as
determined by the VSEL pin and the HW_nSW bit.
Table 5. VOUT Setpoint and Mode Control
MODE_CTRL, CONTROL1[3:2] = 00
VSEL Pin HW_nSW Bit VOUT Setpoint
PFM
0
1
VSEL0
Allowed
1
VSEL1
Per MODE1
x
0
VSEL1
Per MODE1
If HW_nSW = 0, VOUT transitions are initiated through the
following sequence:
1.
Write the new setpoint in VSEL1.
2.
Write desired transition rate in DEFSLEW,
CONTROL2[2:0], and set the GO bit in CONTROL2[7].
If HW_nSW = 1, VOUT transitions are initiated either by
changing the state of the VSEL pin or by writing to the VSEL
register selected by the VSEL pin.
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