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參數(shù)資料
| 型號： | FAB2200UCX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 1.2 W, 2 CHANNEL, AUDIO AMPLIFIER, PBGA25 |
| 封裝： | 0.40 MM PITCH, WLCSP-25 |
| 文件頁數(shù)： | 32/33頁 |
| 文件大?。?/td> | 948K |
| 代理商： | FAB2200UCX |
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2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAB2200 Rev. 1.0.1
8
FAB2200
—
Audio
Subsystem
with
St
ereo
Class-G
Headph
on
eAmplifier
I2C DC Electrical Characteristics
Unless otherwise noted, VBATT = 2.80V to 5.25V and TA = -40°C to 85°C.
Symbol
Parameter
Conditions
Fast Mode (400kHz)
Min.
Max.
Unit
VIL
Low-Level Input Voltage
VBATT 2.80V to 5.25V
-0.3
0.6
V
VIH
High-Level Input Voltage
VBATT 2.80V to 5.25V
1.3
V
VOL
Low-level Output Voltage
at 3mA Sink Current
(Open-Drain or Open-Collector)
0
0.4
V
IIH
High-Level Input Current
Each I/O Pin, Input Voltage = VBATT
-1
1
A
IIL
Low-Level Input Current
Each I/O Pin, Input Voltage = 0V
-1
1
A
I2C AC Electrical Characteristics
Unless otherwise noted, VBATT = 2.80V to 5.25V and TA = -40°C to 85°C.
Symbol
Parameter
Fast Mode
Min.
Max.
Unit
fSCL
SCL Clock Frequency
0
400
kHz
tHD;STA
Hold Time (Repeated) START Condition
0.6
s
tLOW
LOW Period of SCL Clock
1.3
s
tHIGH
HIGH Period of SCL Clock
0.6
s
tSU;STA
Set-up Time for Repeated START Condition
0.6
s
tHD;DAT
Data Hold Time
0
0.9
s
tSU;DAT
Data Set-up Time
(4)
100
ns
tr
Rise Time of SDA and SCL Signals
(5)
20+0.1Cb
300
ns
tf
Fall Time of SDA and SCL Signals
(5)
20+0.1Cb
300
ns
tSU;STO
Set-up Time for STOP Condition
0.6
s
tBUF
Bus Free Time between STOP and START Conditions
1.3
s
tSP
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
0
50
ns
Notes:
4.
A fast-mode I
2C-Bus device can be used in a standard-mode system, but the requirement tSU;DAT ≥250ns must
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line
tr_max + tSU;DAT = 1000 + 250 = 1250ns (according to the standard-mode I
2C bus specification) before the SCL line
is released.
5.
Cb equals the total capacitance of one bus line in pf. If mixed with high-speed mode devices, faster fall times are
allowed according to the I
2C specification.
Figure 3. Definition of Timing for Full-Speed Mode Devices on the I
2C-Bus
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