Revision 10 1-31 Pin Description CLKA/B Routed Clock A and B These pins are clock inputs for clock distribution networks. Input le" />
參數(shù)資料
型號(hào)： EX64-TQ100I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 29/48頁(yè)
文件大?。?/td> 0K
描述： IC FPGA ANTIFUSE 3K 100-TQFP
標(biāo)準(zhǔn)包裝： 90
系列： EX
邏輯元件/單元數(shù)： 128
輸入/輸出數(shù)： 56
門數(shù)： 3000
電源電壓： 2.3 V ~ 2.7 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
eX Family FPGAs
Revision 10
1-31
Pin Description
CLKA/B
Routed Clock A and B
These pins are clock inputs for clock distribution networks. Input levels are compatible with standard TTL
or LVTTL specifications. The clock input is buffered prior to clocking the R-cells. If not used, this pin must
be set LOW or HIGH on the board. It must not be left floating.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hardwired)
Array Clock
This pin is the clock input for sequential modules. Input levels are compatible with standard TTL or
LVTTL specifications. This input is directly wired to each R-cell and offers clock speeds independent of
the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must
not be left floating.
I/O
Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations,
input and output levels are compatible with standard TTL or LVTTL specifications. Unused I/O pins are
automatically tristated by the Designer software.
LP
Low Power Pin
Controls the low power mode of the eX devices. The device is placed in the low power mode by
connecting the LP pin to logic HIGH. In low power mode, all I/Os are tristated, all input buffers are turned
OFF, and the core of the device is turned OFF. To exit the low power mode, the LP pin must be set LOW.
The device enters the low power mode 800 ns after the LP pin is driven to a logic HIGH. It will resume
normal operation 200
s after the LP pin is driven to a logic LOW. LP pin should not be left floating.
Under normal operating condition it should be tied to GND via 10 k
resistor.
NC
No Connection
This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be
left floating with no effect on the operation of the device.
PRA/PRB, I/O
Probe A/B
The Probe pin is used to output data from any user-defined design node within the device. This
diagnostic pin can be used independently or in conjunction with the other probe pin to allow real-time
diagnostic output of any signal path within the device. The Probe pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe capabilities can be permanently disabled to
protect programmed design confidentiality.
TCK, I/O
Test Clock
Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active
when the TMS pin is set LOW (refer to Table 1-4 on page 1-10). This pin functions as an I/O when the
boundary scan state machine reaches the “l(fā)ogic reset” state.
TDI, I/O
Test Data Input
Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS
pin is set LOW (refer to Table 1-4 on page 1-10). This pin functions as an I/O when the boundary scan
state machine reaches the “l(fā)ogic reset” state.
TDO, I/O
Test Data Output
Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW
(refer to Table 1-4 on page 1-10). This pin functions as an I/O when the boundary scan state machine
reaches the "logic reset" state. When Silicon Explorer is being used, TDO will act as an output when the
"checksum" command is run. It will return to user I/O when "checksum" is complete.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EX64-TQ100PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs
EX64-TQ64 功能描述:IC FPGA ANTIFUSE 3K 64-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
EX64-TQ64A 功能描述:IC FPGA ANTIFUSE 3K 64-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
EX64-TQ64I 功能描述:IC FPGA ANTIFUSE 3K 64-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
EX64-TQG100 功能描述:IC FPGA ANTIFUSE 3K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
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