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參數(shù)資料
| 型號： | EX64-FTQ64 |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA ANTIFUSE 3K 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | EX |
| 邏輯元件/單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 41 |
| 門數(shù)： | 3000 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
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eX Family FPGAs
Revision 10
1-11
Table 1-5 describes the different configuration requirements of BST pins and their functionality in different
modes.
TRST Pin
The TRST pin functions as a dedicated Boundary-Scan Reset pin when the Reserve JTAG Test Reset
option is selected, as shown in Figure 1-12. An internal pull-up resistor is permanently enabled on the
TRST pin in this mode. It is recommended to connect this pin to GND in normal operation to keep the
JTAG state controller in the Test-Logic-Reset state. When JTAG is being used, it can be left floating or be
driven HIGH.
When the Reserve JTAG Test Reset option is not selected, this pin will function as a regular I/O. If
unused as an I/O in the design, it will be configured as a tristated output.
JTAG Instructions
Table 1-6 lists the supported instructions with the corresponding IR codes for eX devices.
Table 1-7 lists the codes returned after executing the IDCODE instruction for eX devices. Note that bit 0
is always “1.” Bits 11-1 are always “02F”, which is Microsemi SoC Products Group's manufacturer code.
Table 1-5 Boundary-Scan Pin Configurations and Functions
Mode
Designer "Reserve JTAG" Selection
TAP Controller State
Dedicated (JTAG)
Checked
Any
Flexible (User I/O)
Unchecked
Test-Logic-Reset
Flexible (JTAG)
Unchecked
Any EXCEPT Test-Logic-Reset
Table 1-6 JTAG Instruction Code
Instructions (IR4: IR0)
Binary Code
EXTEST
00000
SAMPLE / PRELOAD
00001
INTEST
00010
USERCODE
00011
IDCODE
00100
HIGHZ
01110
CLAMP
01111
Diagnostic
10000
BYPASS
11111
Reserved
All others
Table 1-7 IDCODE for eX Devices
Device
Revision
Bits 31-28
Bits 27-12
eX64
0
8
40B2, 42B2
eX128
0
9
40B0, 42B0
eX256
0
9
40B5, 42B5
eX64
1
A
40B2, 42B2
eX128
1
B
40B0, 42B0
eX256
1
B
40B5, 42B5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EX64-FTQ64I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:eX Family FPGAs |
| EX64-FTQ64PP | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:eX Family FPGAs |
| EX64-FTQG100 | 功能描述:IC FPGA ANTIFUSE 3K 100-TQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:EX 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| EX64-FTQG100A | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Automotive Family FPGAs |
| EX64-FTQG100I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:eX Family FPGAs |
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