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參數(shù)資料
| 型號(hào)： | EVAL-CONTROLBRD |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| 中文描述： | 18位，2.5 LSB INL和570 kSPS的SAR型ADC |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 1186K |
| 代理商： | EVAL-CONTROLBRD |
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AD7679
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Refer to Figure 32 and Figure 33
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 38 and Figure 39 (Master Serial Interface Modes)
1
CS LOW to SYNC Valid Delay
CS LOW to Internal SCLK Valid Delay
CS LOW to SDOUT Delay
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
2
Internal SCLK Period
2
Internal SCLK HIGH
2
Internal SCLK LOW
2
SDOUT Valid Setup Time
2
SDOUT Valid Hold Time
2
SCLK Last Edge to SYNC Delay
2
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
In Serial Master Read during Convert mode. See
for Serial Master Read after Convert mode.
Table 4
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
10
1.75
10
250
10
20
5
3
25
12
7
4
2
3
5
3
5
5
25
10
10
Typ
2
525
See Table 4
1.5
25
Max
35
1.5
1.5
1.5
45
15
10
10
10
40
10
10
10
18
Unit
ns
μs
ns
μs
ns
ns
μs
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 5 of 28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-CONTROLBRD2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC |
| EVAL-CONTROL-BRD2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer |
| EVAL-CONTROLBRD22 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC |
| EVALCONTROLBRD23 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs |
| EVAL-CONTROLBRD23 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23 |
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