參數(shù)資料
型號(hào)： EVAL-CONTROLBRD
廠商： Analog Devices, Inc.
英文描述： 18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
中文描述： 18位，2.5 LSB INL和570 kSPS的SAR型ADC
文件頁(yè)數(shù)： 24/28頁(yè)
文件大?。?/td> 1186K
代理商： EVAL-CONTROLBRD
AD7679
BUSY
BUSY
#2 (UPSTREAM)
#1 (DOWNSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
BUSY
OUT
03085-0-044
Figure 42. Two AD7679s in a Daisy-Chain Configuration
External Clock Data Read during Conversion
Figure 41 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are low, the result
of the previous conversion can be read. The data is shifted out
MSB first with 18 clock pulses, and is valid on both the rising
and falling edge of the clock. The 18 bits have to be read before
the current conversion is complete. If that is not done,
RDERROR is pulsed high and can be used to interrupt the host
interface to prevent incomplete data reading. There is no daisy-
chain feature in this mode, and the RDC/SDIN input should
always be tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock is recommended to ensure that all bits are
read during the first half of the conversion phase. It is also
possible to begin to read the data after conversion and continue
to read the last bits even after a new conversion has been
initiated.
MICROPROCESSOR INTERFACING
The AD7679 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and for ac signal
processing applications interfacing to a digital signal processor.
The AD7679 is designed to interface either with a parallel 8-bit
or 16-bit wide interface, or with a general-purpose serial port or
I/O ports on a microcontroller. A variety of external buffers can
be used with the AD7679 to prevent digital noise from coupling
into the ADC. The following section illustrates the use of the
AD7679 with an SPI equipped DSP, the ADSP-219x.
SPI Interface (ADSP-219x)
Figure 43 shows an interface diagram between the AD7679 and
the SPI equipped ADSP-219x. To accommodate the slower
speed of the DSP, the AD7679 acts as a slave device, and data
must be read after conversion. This mode also allows the daisy-
chain feature. The convert command could be initiated in
response to an internal timer interrupt. The 18-bit output data
are read with 3-byte SPI access. The reading process could be
initiated in response to the end-of-conversion signal (BUSY
going low) using an interrupt line of the DSP. The serial
interface (SPI) on the ADSP-219x is configured for master
mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase
Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by
writing to the SPI Control register (SPICLTx). It should be
noted that to meet all timing requirements, the SPI clock should
be limited to 17 Mbits/s, which allow it to read an ADC result in
about 1.1 μs. When a higher sampling rate is desired, use of one
of the parallel interface modes is recommended.
AD7679*
ADSP-219x*
SER/PAR
PFx
MISOx
SCKx
PFx or TFSx
BUSY
SDOUT
SCLK
CNVST
EXT/INT
CS
RD
INVSCLK
DVDD
*ADDITIONAL PINS OMITTED FOR CLARITY
SPIxSEL (PFx)
03085-0-045
Figure 43. Interfacing the AD7679 to an SPI Interface
Rev. 0 | Page 24 of 28
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-CONTROLBRD2 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC
EVAL-CONTROL-BRD2 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 1.5 MSPS, 10-Bit and 12-Bit Parallel ADCs with a Sequencer
EVAL-CONTROLBRD22 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, Dual 2 MSPS, 12-Bit, 3-Channel SAR ADC
EVALCONTROLBRD23 制造商:AD 制造商全稱:Analog Devices 功能描述:1.75 MSPS, 4 mW 10-Bit/12-Bit Parallel ADCs
EVAL-CONTROLBRD23 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 555 kSPS, 12-Bit ADC in an 8-Lead SOT-23
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