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參數(shù)資料
| 型號(hào)： | EVAL-CONTROLBRD3 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 16位，100 kSPS的PulSAR系列ADC的，采用MSOP / QFN封裝 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大小： | 467K |
| 代理商： | EVAL-CONTROLBRD3 |
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AD7683
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; T
A
= 40°C to +85°C, unless otherwise noted.
Table 5.
Parameter
Throughput Rate
CS Falling to DCLOCK Low
CS Falling to DCLOCK Rising
DCLOCK Falling to Data Remains Valid
CS Rising Edge to D
OUT
High Impedance
DCLOCK Falling to Data Valid
Acquisition Time
D
OUT
Fall Time
D
OUT
Rise Time
Rev. 0 | Page 5 of 16
Symbol
t
CYC
t
CSD
t
SUCS
t
HDO
t
DIS
t
EN
t
ACQ
t
F
t
R
Min
20
5
400
Typ
16
14
16
11
11
Max
100
0
100
50
25
25
Unit
kHz
μs
ns
ns
ns
ns
ns
ns
ns
0
D
OUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
Hi-Z
0
Hi-Z
t
ACQ
t
DIS
0
1
4
5
t
HDO
t
EN
t
CSD
t
SUCS
t
CYC
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
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相關(guān)代理商/技術(shù)參數(shù) |
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| EVAL-CONTROLBRD32 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 250 kSPS PulSAR?? ADC in MSOP |
| EVAL-CONTROLBRD33 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 2 LSB INL, 3 MSPS PulSAR?? ADC |
| EVAL-CONTROLBRD3Z | 制造商:Analog Devices 功能描述:LINEAR ICS - EVALUATION BOARD |
| EVAL-CONTROLBRD3Z1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 100 kSPS PulSAR, Differential ADC in MSOP |
| EVAL-CONTROLBRD3Z3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC |
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