- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362802 > EVAL-CONTROLBRD3 (Analog Devices, Inc.) 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN PDF資料下載
參數(shù)資料
| 型號： | EVAL-CONTROLBRD3 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN |
| 中文描述： | 16位，100 kSPS的PulSAR系列ADC的，采用MSOP / QFN封裝 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 467K |
| 代理商： | EVAL-CONTROLBRD3 |
AD7683
Table 9. Recommended Driver Amplifiers
Amplifier
Typical Application
AD8021
Very low noise and high frequency
AD8022
Low noise and high frequency
OP184
Low power, low noise, and low frequency
AD8605
,
AD8615
5 V single-supply, low power
AD8519
Small, low power, and low frequency
AD8031
High frequency and low power
Rev. 0 | Page 14 of 16
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
When REF is driven by a very low impedance source (e.g., an unbuffered reference voltage like the low temperature drift
ADR43x
reference or a reference buffer using the
AD8031
or
the
AD8605
), a 10 μF (X5R, 0805 size) ceramic chip capacitor is
appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7683 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery-
powered applications.
1000
100
10
0.1
1
0.01
10
100
1k
10k
100k
0
SAMPLING RATE (SPS)
O
μ
A
VDD = 2.7V
VDD = 5V
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7683 is compatible with SPI, QSPI, digital hosts, and
DSPs (e.g., Blackfin ADSP-BF53x or ADSP-219x). The con-
nection diagram is shown in Figure 25 and the corresponding
timing is given in Figure 2.
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, D
OUT
is enabled and
forced low. The data bits are then clocked, MSB first, by subse-
quent DCLOCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time.
0
CS
DCLOCK
D
OUT
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7683
Figure 25. Connection Diagram
LAYOUT
The printed circuit board housing the AD7683 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7683 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7683 is used as a shield. Fast switching signals, such as CS or
clocks, should never run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog section. In such a case, it
should be joined underneath the AD7683.
The AD7683 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. That is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7683 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7683. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE AD7683’S PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the
evaluation board for the AD7683 (
EVAL-AD7683
). The evalu-
ation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the
EVAL-CONTROL BRD2
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD7705EB | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| EVAL-AD7706EB | 3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| EVAL-AD7707EB | Evaluation Board for the AD7707 3V/5V, +/-10V Input Range, 1mW, 3Channel, 16-Bit, Sigma Delta ADC |
| EVAL-AD7708EB | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| EVAL-AD7718EB | 8-/10-Channel, Low Voltage, Low Power, ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-CONTROLBRD32 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 250 kSPS PulSAR?? ADC in MSOP |
| EVAL-CONTROLBRD33 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 2 LSB INL, 3 MSPS PulSAR?? ADC |
| EVAL-CONTROLBRD3Z | 制造商:Analog Devices 功能描述:LINEAR ICS - EVALUATION BOARD |
| EVAL-CONTROLBRD3Z1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 100 kSPS PulSAR, Differential ADC in MSOP |
| EVAL-CONTROLBRD3Z3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 800 kSPS SAR ADC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。