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參數(shù)資料
| 型號： | EVAL-ADF4360-3EB1 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | XO, clock |
| 英文描述： | Integrated Synthesizer and VCO |
| 中文描述： | 綜合合成器和VCO |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 559K |
| 代理商： | EVAL-ADF4360-3EB1 |
ADF4360-3
Table 7. Control Latch
Rev. 0 | Page 13 of 24
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
PC1
PC2
CR
M1
M2
PDP
CP
CPG
MTLD
PL1
PL2
CPI1
CPI2
CPI3
CP14
CPI5
CPI6
PD1
M3
CONTROL
BITS
MUXOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
PRESCALER
VALUE
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
DB21
DB22
DB23
P
D
P
D
C
R
M
L
C
C
T
S
P
D
P
PD2
P1
P2
CR
0
1
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
PC2
0
0
1
1
0
1
CORE POWERLEVEL
5mA
10mA
15mA
20mA
PC1
0
1
CP
0
1
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
PDP
0
1
PHASE DETECTOR
POLARITY
NEGATIVE
POSITIVE
CPG
0
1
CP GAIN
CURRENT SETTING 1
CURRENT SETTING 2
MTLD
0
1
MUTE-TILL-LOCK DETECT
DISABLED
ENABLED
M3
0
0
M2
0
0
M1
0
1
OUTPUT
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATAOUTPUT
DGND
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
0
1
P2
0
0
1
1
P1
0
1
0
1
PRESCALER VALUE
8/9
16/17
32/33
32/33
CE PIN
0
1
1
1
PD2
X
X
0
1
PD1
X
0
1
1
MODE
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CPI6
CPI3
0
0
0
0
1
1
1
1
CPI5
CPI2
0
0
1
1
0
0
1
1
CPI4
CPI1
0
1
0
1
0
1
0
1
I
CP
(mA)
4.7k
0.31
0.62
0.93
1.25
1.56
1.87
2.18
2.50
PL2
PL1
OUTPUT POWER LEVEL
CURRENT
3.5mA
5.0mA
7.5mA
11.0mA
POWER INTO 50
(USING 50
TO V
CC
)
–12
dBm
–9
dBm
–6
dBm
–3
dBm
0
0
1
1
0
1
0
1
0
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相關代理商/技術參數(shù) |
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| EVAL-ADF4360-4EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
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| EVAL-ADF4360-6EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Integrated Synthesizer and VCO |
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