參數(shù)資料
型號: EVAL-ADF4360-3EB1
廠商: Analog Devices, Inc.
元件分類: XO, clock
英文描述: Integrated Synthesizer and VCO
中文描述: 綜合合成器和VCO
文件頁數(shù): 1/24頁
文件大?。?/td> 559K
代理商: EVAL-ADF4360-3EB1
Integrated Synthesizer and VCO
ADF4360-3
FEATURES
Rev.
0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Tel: 781.329.4700
www.analog.com
Output frequency range: 1600 MHz to 1950 MHz
Divide-by-2 output
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable dual-modulus prescaler 8/9, 16/17, 32/33
Programmable output power level
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
APPLICATIONS
Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-3 is a fully integrated integer-N synthesizer and
voltage controlled oscillator (VCO). The ADF4360-3 is designed
for a center frequency of 1750 MHz. In addition, there is a
divide-by-2 option available, whereby the user gets an RF out-
put of between 800 MHz and 975 MHz.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging from
3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
V
VCO
V
TUNE
REF
IN
CLK
DATA
LE
AV
DD
DV
DD
CE
AGND
DGND
CPGND
R
SET
C
C
C
N
RF
OUT
A
RF
OUT
B
VCO
PHASE
COMPARATOR
MUTE
DIVSEL = 2
DIVSEL = 1
N = (BP + A)
LOAD
LOAD
CHARGE
PUMP
STAGE
M
INTEGER
REGISTER
13-BIT B
COUNTER
14-BIT R
COUNTER
24-BIT
FUNCTION
LATCH
24-BIT
DATA REGISTER
5-BIT A
COUNTER
PRESCALER
P/P+1
MULTIPLEXER
LOCK
DETECT
÷
2
ADF4360-3
0
Figure 1.
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