參數(shù)資料
型號(hào)： EVAL-ADE7763EB
廠商： Analog Devices, Inc.
英文描述： Single-Phase Active and Apparent Energy Metering IC
中文描述： 單相有功功率和視在電能計(jì)量IC
文件頁(yè)數(shù)： 50/56頁(yè)
文件大?。?/td> 1328K
代理商： EVAL-ADE7763EB
ADE7763
REGISTER DESCRIPTIONS
All ADE7763 functionality is accessed via on-chip registers. Each r
ansf ring the regis
data. full descr tion of the se
then tr
er
ter
Rev. A | Page 50 of 56
ister and
l int
col is given in the Serial Interface section.
MU
omm
N R
egis
T
is an
bit, write
8-
regist
at con
processor. All data transfer operations must begin with a write to t
r det
wheth
the n t operation is a read o
designations for the communication register.
write
r a
DB7
W/R
DB6
0
DB5
A5
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
egister is accessed by first writing to the communication reg
erface proto
A
ip
ria
COM
The c
NICATIO
unication r
EGIS ER
ter
-only
er th
trols the serial data transfer between the ADE7763 and the host
he communication register. The data written to the communication
and which register is being accessed. Table 10 outlines the bit
registe
ermines
er
ex
Table 10. Communication Register
Bit
Location
Mnemonic
0 to 5
A0 to A5
Bit
Description
The 6 LSBs of the communication register specify the register for the data transfer operation. Table 9 lists the
address of each on-chip register.
This bit is unused and should be set to 0.
When this bit is a Logic 1, the data transfer operation immediately following the write to the communication
register is interpreted as a write to the ADE7763. When this bit is a Logic 0, the data transfer operation
immediately following the write to the communication register is interpreted as a read operation.
6
7
RESERVED
W/R
MODE REGISTER (0x09)
The ADE7763 functionality is configured by writing to the mode register. Table 11 describes the functionality of each bit
in the register.
Table 11.
Bit
Location
Mnemonic
Value
Description
0
DISHPF
0
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
1
DISLPF2
0
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
2
DISCF
1
Frequency output CF is disabled when this bit is set.
3
DISSAG
1
Line voltage sag detection is disabled when this bit is set.
4
ASUSPEND
0
By setting this bit to Logic 1, both A/D converters can be turned off. During normal operation, this
bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock
signal at CLKIN pin.
5
TEMPSEL
0
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 after the
temperature conversion.
6
SWRST
0
Software Chip Reset. A data transfer should not take place to the ADE7763 for at least 18 μs after
a software reset.
7
CYCMODE
0
Setting this bit to Logic 1 places the chip in line cycle energy accumulation mode.
8
DISCH1
0
ADC 1 (Channel 1) inputs are internally shorted together.
9
DISCH2
0
ADC 2 (Channel 2) inputs are internally shorted together.
10
SWAP
0
By setting this bit to Logic 1, the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
Use these bits to select the waveform register update rate.
DTRT1
DTRT0
0
0
0
1
1
0
1
1
Bit
Default
Update Rate
27.9 kSPS (CLKIN/128)
14 kSPS (CLKIN/256)
7 kSPS (CLKIN/512)
3.5 kSPS (CLKIN/1024)
12, 11
DTRT1, 0
00
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