- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362803 > EVAL-ADE7763EB (Analog Devices, Inc.) Single-Phase Active and Apparent Energy Metering IC PDF資料下載
參數(shù)資料
| 型號(hào)： | EVAL-ADE7763EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Single-Phase Active and Apparent Energy Metering IC |
| 中文描述： | 單相有功功率和視在電能計(jì)量IC |
| 文件頁數(shù)： | 45/56頁 |
| 文件大?。?/td> | 1328K |
| 代理商： | EVAL-ADE7763EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
ADE7763
The serial interface of the ADE7763 is m
SCLK, DIN, DOUT, and CS. The serial clock for a data transfer
is applied at the SCLK logic input. This logic input has a Schmitt-
trigger input structure that allows slow rising and falling clo
edges to be used. All data transfer operations are synchronized
to the serial clock. Data is shifted into the ADE7763 at the DIN
logic input upon the falling edge of SCLK. Data is shifted out o
the ADE7763 at the DOUT logic output upon a rising edge o
SCLK. The
CS logic input is the chip-select input. This input is
used when
multiple devices share the serial bus. A falling edge
upon CS also resets the serial in
into communication mode. T
he CS input should be driven low
for the entire data transfer operation. Bringing CS high during a
data transfer operation aborts the transfer and places the serial
bus in a high impedance state. The CS logic input can be tied
low if the ADE7763 is the only device on the serial bus. However,
with CS tied low, all initiated data transfer operations must be
fully completed, i.e., the LSB of each register must be transferred
because there is no other way to bring the ADE7763 into commu-
nication mode without resetting the entire device using RESET.
ADE7763 Serial Write Operation
The serial write sequence takes place as follows. With the
ADE7763 in communication mode (i.e., the CS input logic low),
first a write to the communication register occurs. The MSB of
this byte transfer is a 1, indicating that the data transfer
operation is a write. The LSBs of this byte contain the address of
Rev. A | Page 45 of 56
ade up of four signals:
ck
f
f
terface and places the ADE7763
the register to be written to. The ADE7763 starts shifting in the
register data upon the next falling edge of SCLK. All remaining
bits of register data are shifted in upon the falling edge of
subsequent SCLK pulses—see Figure 83. As explained earlier,
the data write is initiated by a write to the communication
register followed by the data. During a data write operation,
data is transferred to all on-chip registers one byte at a time.
After a byte is transferred into the serial port, there is a finite
time before it is transferred to one of the ADE7763 on-chip
registers. Although another byte transfer to the serial port can
start while the previous byte is being transferred to an on-chip
register, this second byte transfer should not finish until at least
4 μs after the end of the previous byte transfer. This functionality
is expressed in the timing specification t
6
—see Figure 83. I
w
rite operation is aborted during a byte transfer (CS is brought
high), then that byte cannot be written to the destination register.
f a
Destination registers can be up to 3 bytes wide—see Table 9,
Table 10, Table 11, Table 12, and Table 13. Therefore the first
byte shifted into the serial port at DIN is transferred to the MSB
(most significant byte) o
f the destination register. If, for example,
the addressed register is 12 bits wide, a 2-byte data transfer
must take place. Because the data is always assumed to be right
justified, in this case the 4 MSBs of the first byte would be
ignored and the 4 LSBs of the first byte written to the ADE776
would be the 4 MSBs of the 12-bit word. Figure 84 illustrates
this example.
3
DIN
SCLK
t
2
t
3
t
4
t
5
COMMAND BYTE
1
0
A4
A5
A3
A2
A1
A0
CS
t
1
t
7
t
6
t
8
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
DB7
DB0
DB7
DB0
t
7
0
Interface Write Timing
Figure 83. Serial
SCLK
DIN
X
X
X
X
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
MOST SIGNIFICANT BYTE
LEAST SIGNIFICANT BYTE
0
Figure 84. 12-Bit Serial Write Operation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-ADF4112EB1 | CDMA Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF4113EB1 | GSM900 Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF4113EB2 | 1750MHz Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF4118EB1 | WCDMA Evaluation Board For PLL Frequency Synthesizer |
| EVAL-ADF411XEB1 | Hook-Up Wire; Conductor Size AWG:22; No. Strands x Strand Size:7 x 30; Jacket Color:Orange; Cable/Wire MIL SPEC:MIL-W-76C Type MW; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC); Leaded Process Compatible:Yes RoHS Compliant: Yes |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-ADE7763ZEB | 功能描述:BOARD EVALUATION FOR ADE7763 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADE7816EBZ | 功能描述:BOARD EVALUATION FOR ADE7816 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-ADE7854EBZ | 制造商:Analog Devices 功能描述:EVALUATION BOARDS - Boxed Product (Development Kits) |
| EVAL-ADE7858EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Poly Phase Multifunction Energy Metering IC with per Phase Active and Reactive Powers |
| EVAL-ADE7878EBZ | 功能描述:BOARD EVAL FOR ADE7878 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。