參數(shù)資料
型號(hào): EVAL-AD7983SDZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 8/24頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD7983
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
ADC 的數(shù)量: 1
位數(shù): 16
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
輸入范圍: 0 ~ VREF
在以下條件下的電源(標(biāo)準(zhǔn)): 10.5mW @ 1.33MSPS
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7983
已供物品:
AD7983
Rev. A | Page 16 of 24
DIGITAL INTERFACE
Though the AD7983 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7983 is compatible with SPI, QSPI,
and digital hosts. This interface can use either a 3-wire or a 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections useful, for instance, in
isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
The AD7983, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
In either mode, the AD7983 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled
In CS mode if CNV or SDI is low when the ADC conversion
ends (see
and
).
In chain mode if SCK is high during the CNV rising edge
(see Figure 37).
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