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參數(shù)資料
| 型號(hào)： | EVAL-AD7983SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7983 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1.33M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | 0 ~ VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 10.5mW @ 1.33MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7983 |
| 已供物品： | 板 |
AD7983
Rev. A | Page 18 of 24
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input.
The connection diagram is shown in Figure 28, and the
corresponding timing is given in Figure 29.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data read back controlled by the
digital host. The AD7983 then enters the acquisition phase and
goes into standby mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
If multiple AD7983s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended that this contention be
kept as short as possible to limit extra power dissipation.
AD7983 SDO
SDI
DATA IN
IRQ
DIGITAL HOST
CONVERT
CLK
VIO
47k
CNV
SCK
06
97
4-
01
4
Figure 28. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
tCONV
tCNVH
tCYC
ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCK
CNV
SDI = 1
SDO
D15
D14
D1
D0
tHSDO
12
3
15
16
17
tDSDO
tDIS
06
97
4-
0
15
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
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