參數(shù)資料
型號： EVAL-AD7944EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 14/28頁
文件大小： 0K
描述： BOARD EVAL FOR AD7944
標準包裝： 1
系列： PulSAR®
ADC 的數(shù)量： 1
位數(shù)： 14
采樣率（每秒）： 2.5M
數(shù)據(jù)接口： SPI?、QSPI?、MICROWIRE? 和 DSP
輸入范圍： 0 ~ 5 V
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD7944
已供物品： 板
AD7944
Rev. A | Page 21 of 28
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7944 devices are
connected to an SPI-compatible digital host. A connection dia-
gram example using two AD7944 devices is shown in Figure 30,
and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase
and the subsequent data readback. (If SDI and CNV are low,
SDO is driven low.) Prior to the minimum conversion time,
SDI can be used to select other SPI devices, such as analog multi-
plexers, but SDI must be returned high before the minimum
conversion time elapses and then held high for the maximum
possible conversion time to avoid the generation of the busy
signal indicator.
When the conversion is complete, the AD7944 enters the
acquisition phase and, if the part is in normal mode (TURBO
low), powers down. Each ADC result can be read by bringing its
SDI input low, which consequently outputs the MSB onto SDO.
The remaining data bits are then clocked by subsequent SCK
falling edges. The data is valid on both SCK edges. Although the
rising edge can be used to capture the data, a digital host using
the SCK falling edge allows a faster reading rate, provided that it
has an acceptable hold time. After the 14th SCK falling edge, SDO
returns to high impedance and another AD7944 can be read.
AD7944
SDI
SDO
CNV
SCK
CONVERT
DATA IN
CLK
DIGITAL HOST
CS1
CS2
AD7944
SDI
SDO
CNV
SCK
04658-
013
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
ACQUISITION (n)
ACQUISITION
(n – 1)
ACQUISITION
(n + 1)
1
2
BEGIN DATA (n – 1)
CONVERSION (n)
END DATA (n – 1)
SCK
CNV
SDO
12
13
CONVERSION (n – 1)
END DATA (n – 2)
tCONV
tDATA
0
(I/O QUIET
TIME)
(I/O QUIET
TIME)
14
12
13
14
1
13
12
11
2
0
1
2
SDI
(I/O QUIET
TIME)
tCYC
tACQ
tQUIET
tSCK
tDIS
tHSDO
tHSDICNV
tSSDICNV
tEN
tDSDO
tHSDO
tDATA
tCONV
04658-
014
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
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