參數(shù)資料
型號(hào)： EVAL-AD7859CB
廠商： Analog Devices, Inc.
英文描述： 3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADCs
中文描述： 3 V至5 V單電源，200 kSPS的8通道，12位采樣ADC
文件頁數(shù)： 4/28頁
文件大?。?/td> 535K
代理商： EVAL-AD7859CB
AD7859/AD7859L
TIMING SPECIFICATIONS
1
(AV
DD
= DV
DD
= +3.0 V to +5.5 V; f
CLKIN
= 4 MHz for AD7859 and 1.8 MHz for AD7859L;
T
A
= T
MIN
to T
MAX
, unless otherwise noted)
REV. A
–4–
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter
5 V
3 V
Units
Description
f
CLKIN2
500
4
1.8
100
50
4.5
10
15
5
0
0
55
50
5
40
60
0
5
0
0
55
10
5
1/2 t
CLKIN
2.5 t
CLKIN
31.25
500
4
1.8
100
90
4.5
10
15
5
0
0
55
50
5
40
70
0
5
0
0
70
10
5
1/2 t
CLKIN
2.5 t
CLKIN
31.25
kHz min
MHz max
MHz max
ns min
ns max
μ
s max
μ
s max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ms typ
Master Clock Frequency
L Version
CONVST
Pulse Width
CONVST
to BUSY
↑
Propagation Delay
Conversion Time = 18 t
CLKIN
L Version 1.8 MHz CLKIN. Conversion Time = 18 t
CLKIN
HBEN to RD Setup Time
HBEN to RD Hold Time
CS
to
RD
to Setup Time
CS
to
RD
Hold Time
RD
Pulse Width
Data Access Time After
RD
Bus Relinquish Time After
RD
Bus Relinquish Time After
RD
Minimum Time Between Reads
HBEN to
WR
Setup Time
HBEN to
WR
Hold Time
CS
to
WR
Setup Time
CS
to
WR
Hold Time
WR
Pulse Width
Data Setup Time Before WR
Data Hold Time After WR
New Data Valid Before Falling Edge of BUSY
CS
↑
to BUSY
↑
in Calibration Sequence
Full Self-Calibration Time, Master Clock Dependent (125013
t
CLKIN
)
Internal DAC Plus System Full-Scale Cal Time, Master Clock
Dependent (111124 t
CLKIN
)
System Offset Calibration Time, Master Clock Dependent
(13889 t
CLKIN
)
t
13
t
2
t
CONVERT
t
3
t
4
t
5
t
6
t
7
t
84
t
95
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
t
17
t
19
t
CAL6
t
CAL16
27.78
27.78
ms typ
t
CAL26
3.47
3.47
ms typ
NOTES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
Mark/Space ratio for the master clock input is 40/60 to 60/40.
3
The
CONVST
pulse width will here only apply for normal operation. When the part is in power-down mode, a different
CONVST
pulse width will apply (see Power-
Down section).
4
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
5
t
9
is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
9
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6
The typical time specified for the calibration times is for a master clock of 4 MHz. For the L version the calibration times will be longer than those quoted here due to
the 1.8 MHz master clock.
Specifications subject to change without notice.
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