參數(shù)資料
型號： EVAL-AD7854CB
廠商： Analog Devices, Inc.
英文描述： 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs
中文描述： 3 V至5 V單電源，200 kSPS的12位采樣ADC
文件頁數(shù)： 3/28頁
文件大?。?/td> 264K
代理商： EVAL-AD7854CB
Parameter
A Version
1
B Version
1
S Version
1
Units
Test Conditions/Comments
POWER REQUIREMENTS
AV
DD,
DV
DD
I
DD
Normal Mode
5
+3.0/+5.5
+3.0/+5.5
+3.0/+5.5
V min/max
5.5 (1.8)
5.5 (1.8)
6 (1.8)
mA max
AV
DD
= DV
DD
= 4.5 V to 5.5 V. Typically 4.5 mA
(1.5 mA);
AV
DD
= DV
DD
= 3.0 V to 3.6 V. Typically 4.0 mA
(1.5 mA).
5.5 (1.8)
5.5 (1.8)
6 (1.8)
mA max
Sleep Mode
6
With External Clock On
10
10
10
μ
A typ
Full power-down. Power management bits in control
register set as PMGT1 = 1, PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
Typically 1
μ
A. Full power-down. Power management
bits in control register set as PMGT1 = 1,
PMGT0 = 0.
Partial power-down. Power management bits in
control register set as PMGT1 = 1, PMGT0 = 1.
V
DD
= 5.5 V: Typically 25 mW (8)
V
DD
= 3.6 V: Typically 15 mW (5.4)
400
400
400
μ
A typ
With External Clock Off
5
5
5
μ
A max
200
200
200
μ
A typ
Normal Mode Power Dissipation
30 (10)
20 (6.5)
30 (10)
20 (6.5)
30 (10)
20 (6.5)
mW max
mW max
Sleep Mode Power Dissipation
With External Clock On
55
36
27.5
18
55
36
27.5
18
55
36
27.5
18
μ
W typ
μ
W typ
μ
W max
μ
W max
V
DD
= 5.5 V
V
DD
= 3.6 V
V
DD
= 5.5 V: Typically 5.5
μ
W
V
DD
= 3.6 V: Typically 3.6
μ
W
With External Clock Off
SYSTEM CALIBRATION
Offset Calibration Span
7
Gain Calibration Span
7
+0.05
×
V
REF
/–0.05
×
V
REF
+0.025
×
V
REF
/–0.025
×
V
REF
V max/min
V max/min
Allowable Offset Voltage Span for Calibration
Allowable Full-Scale Voltage Span for Calibration
NOTES
1
Temperature ranges as follows: A, B Versions, –40
°
C to +85
°
C; S Version, –55
°
C to +125
°
C.
2
Specifications apply after calibration.
3
Not production tested. Guaranteed by characterization at initial product release.
4
Sample tested @ +25
°
C to ensure compliance.
5
All digital inputs @ DGND except for
CONVST
@ DV
. No load on the digital outputs. Analog inputs @ AGND.
6
CLKIN @ DGND when external clock off. All digital inputs @ DGND except for
CONVST
@ DV
. No load on the digital outputs. Analog inputs @ AGND.
7
The offset and gain calibration spans are defined as the range of offset and gain errors that the AD7854/AD7854L can calibrate. Note also that these are voltage spans
and are not absolute voltages (i.e., the allowable system offset voltage presented at AIN(+) for the system offset error to be adjusted out will be AIN(–)
±
0.05
×
V
REF
,
and the allowable system full-scale voltage applied between AIN(+) and AIN(–) for the system full-scale voltage error to be adjusted out will be V
REF
±
0.025
×
V
REF
(unipolar mode) and V
REF
/2
±
0.025
×
V
REF
(bipolar mode)). This is explained in more detail in the calibration section of the data sheet.
Specifications subject to change without notice.
REV. B
–3–
AD7854/AD7854L
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