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參數(shù)資料
| 型號(hào)： | EVAL-AD7712EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 0.1UF 50V +-20% 0805 X7R CERAMIC CAPACITOR |
| 中文描述： | LC2MOS信號(hào)調(diào)理模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 229K |
| 代理商： | EVAL-AD7712EB |
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REV. E
–22–
AD7712
Figure 13a shows a read operation from the AD7712 where
RFS
remains low for the duration of the data word transmission.
With
DRDY
low, the
RFS
input is brought low. The input
SCLK signal should be low between read and write operations.
RFS
going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the
DRDY
line high. This rising edge of
DRDY
turns off
the serial data output.
Figure 13b shows a timing diagram for a read operation where
RFS
returns high during the transmission of the word and re-
turns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when
RFS
returns high in the middle
of transferring a word.
RFS
should return high during a low time of SCLK. On the
rising edge of
RFS
, the SDATA output is turned off.
DRDY
remains low and will remain low until all bits of the data word
are read from the AD7712, regardless of the number of times
RFS
changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS
, the next bit (BIT N + 1) may appear on the databus be-
fore
RFS
goes high. When
RFS
returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY
line will go high, turning off the SDATA output as per
Figure 13a.
RFS
(I)
SCLK (I)
SDATA (O)
LSB
MSB
THREE-STATE
A0 (I)
DRDY
(O)
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
Figure 13a. External Clocking Mode, Output Data Read Operation
THREE-STATE
MSB
BIT N
BIT N+1
SDATA (O)
SCLK (I)
RFS
(I)
A0 (I)
DRDY
(O)
t
20
t
22
t
26
t
24
t
25
t
27
t
31
t
24
t
25
t
30
Figure 13b. External Clocking Mode, Output Data Read Operation (
RFS
Returns High During Read Operation)
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PDF描述 |
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| EVAL-AD7713EB | CAP CERAMIC 1.0UF 10V 10% X7R 0805 SMD |
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| EVAL-AD7715-3EB | 3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7713EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS Loop-Powered Signal Conditioning ADC |
| EVAL-AD7714-3EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk |
| EVAL-AD7714-3EBZ | 功能描述:BOARD EVAL FOR AD7714 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7714-5EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk |
| EVAL-AD7715-3EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 450 uA 16-Bit, Sigma-Delta ADC |
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