參數(shù)資料
型號(hào)： EVAL-AD7677CB
廠商： Analog Devices, Inc.
英文描述： 16-Bit, 1 LSB INL, 1 MSPS Differential ADC
中文描述： 16位，1 LSB INL和1 MSPS的差分ADC
文件頁(yè)數(shù)： 17/20頁(yè)
文件大?。?/td> 322K
代理商： EVAL-AD7677CB
REV. 0
AD7677
–17–
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion, or during
the following conversion.
Figure 17 and Figure 18 show the detailed timing diagrams of
these two modes.
Usually, because the AD7677 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
serial mode when it can be used.
In read-after-conversion mode, it should be noted that, unlike in
other modes, the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase which
results in a longer BUSY width.
In read-during-conversion mode, the serial clock and data toggle at
appropriate instances minimizes potential feedthrough between
digital activity and the critical conversion decisions.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
SLAVE SERIAL INTERFACE
External Clock
The AD7677 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT
pin is held
high. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS
and the data are
output when both
CS
and
RD
are low. Thus, depending on
CS
,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous
or discontinuous clock. A discontinuous clock can be either
normally high or normally low when inactive. Figure 19 and
Figure 20 show the detailed timing diagrams of these methods.
While the AD7677 is performing a bit decision, it is important that
voltage transients not occur on digital input/output pins or degra-
dation of the conversion result could occur. This is particularly
important during the second half of the conversion phase because
the AD7677 provides error correction circuitry that can correct for
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
X15
X14
X
1
2
3
14
15
16
17
18
EXT/
INT
= 1
RD
= 0
t
35
t
36
t
37
t
31
t
32
t
34
t
16
t
33
Figure 19. Slave Serial Data Timing for Reading (Read After Convert)
CNVST
SDOUT
SCLK
D1
D0
X
D15
D14
D13
1
2
3
14
15
16
BUSY
INVSCLK = 0
CS
EXT/
INT
= 1
RD
= 0
t
35
t
36
t
37
t
31
t
32
t
16
t
3
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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