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| 型號： | EVAL-AD7606EDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7606 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 在以下條件下的電源（標準）： | 100mW @ 200kSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7606 |
| 已供物品： | 板 |
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Data Sheet
AD7606/AD7606-6/AD7606-4
Rev. C | Page 29 of 36
DIGITAL FILTER
The AD7606/AD7606-6/AD7606-4 contain an optional digital
first-order sinc filter that should be used in applications where
slower throughput rates are used or where higher signal-to-noise
ratio or dynamic range is desirable. The oversampling ratio of the
digital filter is controlled using the oversampling pins, OS [2:0] (see
Table 9). OS 2 is the MSB control bit, and OS 0 is the LSB control
bit. Table 9 provides the oversampling bit decoding to select the
different oversample rates. The OS pins are latched on the falling
edge of BUSY. This sets the oversampling rate for the next
conversion (see Figure 48). In addition to the oversampling
function, the output result is decimated to 16-bit resolution.
If the OS pins are set to select an OS ratio of eight, the next
CONVST x rising edge takes the first sample for each channel,
and the remaining seven samples for all channels are taken with
an internally generated sampling signal. These samples are then
averaged to yield an improvement in SNR performance. Table 9
shows typical SNR performance for both the ±10 V and the ±5 V
range. As Table 9 shows, there is an improvement in SNR as the
OS ratio increases. As the OS ratio increases, the 3 dB frequency
is reduced, and the allowed sampling frequency is also reduced.
In an application where the required sampling frequency is
10 kSPS, an OS ratio of up to 16 can be used. In this case, the
application sees an improvement in SNR, but the input 3 dB
bandwidth is limited to ~6 kHz.
The CONVST A and CONVST B pins must be tied/driven
together when oversampling is turned on. When the over-
sampling function is turned on, the BUSY high time for the
conversion process extends. The actual BUSY high time
depends on the oversampling rate that is selected: the higher the
oversampling rate, the longer the BUSY high, or total conversion
time (see Table 3).
08479-
046
CS
RD
DATA:
DB[15:0]
BUSY
CONVST A
AND
CONVST B
tCYCLE
tCONV
4s
t4
9s
19s
OS = 0 OS = 2 OS = 4
Figure 47. AD7606—No Oversampling, Oversampling × 2, and
Oversampling × 4 While Using Read After Conversion
Figure 47 shows that the conversion time extends as the over-
sampling rate is increased, and the BUSY signal lengthens for the
different oversampling rates. For example, a sampling frequency
of 10 kSPS yields a cycle time of 100 s. Figure 47 shows OS × 2
and OS × 4; for a 10 kSPS example, there is adequate cycle time to
further increase the oversampling rate and yield greater improve-
ments in SNR performance. In an application where the initial
sampling or throughput rate is at 200 kSPS, for example, and
oversampling is turned on, the throughput rate must be reduced
to accommodate the longer conversion time and to allow for the
read. To achieve the fastest throughput rate possible when over-
sampling is turned on, the read can be performed during the
BUSY high time. The falling edge of BUSY is used to update the
output data registers with the new conversion data; therefore, the
reading of conversion data should not occur on this edge.
CONVST A
AND
CONVST B
BUSY
OS x
tOS_SETUP
tOS_HOLD
CONVERSION N
CONVERSION N + 1
OVERSAMPLE RATE
LATCHED FOR CONVERSION N + 1
08479-
045
Figure 48. OS x Pin Timing
Table 9. Oversample Bit Decoding
OS[2:0]
OS
Ratio
SNR 5 V Range
(dB)
SNR 10 V Range
(dB)
3 dB BW 5 V Range
(kHz)
3 dB BW 10 V Range
(kHz)
Maximum Throughput
CONVST Frequency (kHz)
000
No OS
89
90
15
22
200
001
2
91.2
92
15
22
100
010
4
92.6
93.6
13.7
18.5
50
011
8
94.2
95
10.3
11.9
25
100
16
95.5
96
6
12.5
101
32
96.4
96.7
3
6.25
110
64
96.9
97
1.5
3.125
111
Invalid
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