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參數(shù)資料
| 型號(hào)： | EVAL-AD7298SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/25頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7298 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，串行，SPI? |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD7298 |
| 已供物品： | 板，纜線，CD |
AD7298
Rev. B | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 2.8 V to 3.6 V; VDRIVE = 1.65 V to 3.6 V; VREF = 2.5 V internal; TA = 40°C to + 125°C, unless otherwise noted. Sample tested during
initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level
of 1.6 V.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Test Conditions/Comments
tCONVERT
t2 + (16 × tSCLK)
μs max
Conversion time
820
ns typ
Each ADC channel VIN0 to VIN7, fSCLK = 20 MHz
100
μs max
Temperature sensor channel
50
kHz min
Frequency of external serial clock
20
MHz max
Frequency of external serial clock
tQUIET
6
ns min
Minimum quiet time required between the end of serial read and the start
of the next voltage conversion in repeat and nonrepeat mode.
t2
10
ns min
CS to SCLK setup time
t31
15
ns max
Delay from CS (falling edge) until DOUT three-state disabled
t41
Data access time after SCLK falling edge
35
ns max
VDRIVE = 1.65 V to 3 V
28
ns max
VDRIVE = 3 V to 3.6 V
t5
0.4 × tSCLK
ns min
SCLK low pulse width
t6
0.4 × tSCLK
ns min
SCLK high pulse width
t71
14
ns min
SCLK to DOUT valid hold time
t81
16/34
ns min/max
SCLK falling edge to DOUT high impedance
t9
5
ns min
DIN setup time prior to SCLK falling edge
t10
4
ns min
DIN hold time after SCLK falling edge
t11
100
ns min
TSENSE_BUSY falling edge to CS falling edge
t121
30
ns max
Delay from CS rising edge to DOUT high impedance
tPOWER-UP_PARTIAL
1
μs max
Power-up time from partial power-down
tPOWER-UP
6
ms max
Internal reference power-up time from full power-down
1 Measured with a load capacitance on DOUT of 15 pF.
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參數(shù)描述 |
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