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| 型號(hào)： | EVAL-AD7150EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 23/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7150 |
| 特色產(chǎn)品： | AD715x Series Capacitance-to-Digital Converters & Evaluation Board |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 傳感器類型： | 觸摸，電容式 |
| 接口： | I²C |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 嵌入式： | 否 |
| 已供物品： | 板，電池 |
| 已用 IC / 零件： | AD7150 |
| 產(chǎn)品目錄頁(yè)面： | 781 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD7150BRMZ-REEL-ND - IC CAP CONV 2CH ULT LP 10MSOP AD7150BRMZ-ND - IC CAP CONV 2CH ULT LP 10MSOP |
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AD7150
Rev. 0 | Page 4 of 28
Parameter
Min
Typ
Max
Unit1
Test Conditions/Comments
POWER REQUIREMENTS
VDD-to-GND Voltage
2.7
3.6
V
VDD = 3.3 V, nominal
100
120
μA
1
5
μA
Temperature ≤ 25°C
3
10
μA
Temperature = 85°C
1 Capacitance units: one picofarad (1 pF) = 1 × 1012 farad (F); one femtofarad (1 fF) = 1015 farad (F).
2 The CAPDAC can be used to shift (offset) the input range. The total capacitance of the sensor can therefore be up to the sum of the CAPDAC value and the conversion
input range. With the autoCAPDAC feature, the CAPDAC is adjusted automatically when the CDC input value is lower than 25% or higher than 75% of the CDC
nominal input range.
3 Specification is not production tested but is supported by characterization data at initial product release.
4 Digital inputs equal to VDD or GND.
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
CONVERTER
Conversion Time
10
ms
Both channels, 5 ms per channel.
0.15
ms
2
ms
2
ms
See Figure 2.
SCL Frequency
0
400
kHz
SCL High Pulse Width, tHIGH
0.6
μs
SCL Low Pulse Width, tLOW
1.3
μs
SCL, SDA Rise Time, tR
0.3
μs
SCL, SDA Fall Time, tF
0.3
μs
Hold Time (Start Condition), tHD;STA
0.6
μs
After this period, the first clock is generated.
Setup Time (Start Condition), tSU;STA
0.6
μs
Relevant for repeated start condition.
Data Setup Time, tSU;DAT
0.1
μs
Setup Time (Stop Condition), tSU;STO
0.6
μs
Data Hold Time (Master), tHD;DAT
10
ns
Bus-Free Time (Between Stop and Start Condition), tBUF
1.3
μs
1 Specification is not production tested but is supported by characterization data at initial product release.
2 Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
3 Power-up time is the maximum delay between the VDD crossing the minimum level (2.7 V) and either the start of conversion or when ready to receive a serial interface
command.
4 Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial interface
command.
5 Sample tested during initial release to ensure compliance.
6 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
P
S
tLOW
tR
tF
tHD;STA
tHD;DAT
tSU;DAT
tSU;STA
tHD;STA
tSU;STO
tHIGH
SCL
PS
SDA
06
51
7-
00
2
tBUF
Figure 2. Serial Interface Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7150EBZ | 制造商:Analog Devices 功能描述:PROXIMITY SENSOR EVAL BOARD |
| EVAL-AD7152EBZ | 功能描述:BOARD EVAL AD7152 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 傳感器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- |
| EVAL-AD7156EBZ | 功能描述:BOARD EVAL FOR AD7156 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 傳感器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- |
| EVAL-AD7156EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD7156 2CH CAPACITANCE CONVE |
| EVAL-AD7170EBZ | 功能描述:BOARD EVAL FOR AD7170 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
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