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參數(shù)資料
| 型號(hào)： | EVAL-AD5821EBZ1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 120 mA, Current Sinking, 10-Bit, I2C DAC |
| 中文描述： | 120毫安，灌電流，10位和I2C數(shù)模轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大小： | 386K |
| 代理商： | EVAL-AD5821EBZ1 |
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AD5821
AC SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance R
L
= 25 Ω connected to V
DD
, unless otherwise noted.
Rev. 0 | Page 4 of 16
Table 2.
Parameter
Output Current Settling Time
Slew Rate
Major Code Change Glitch Impulse
Digital Feedthrough
3
B Version
1, 2
Min
Typ
250
0.3
0.15
0.06
Unit
μs
mA/μs
nA-s
nA-s
Test Conditions/Comments
V
DD
= 3.6 V, R
L
= 25 Ω, L
L
= 680 μH, scale to scale change (0x100 to 0x300)
1 LSB change around major carry
Max
1
Temperature range is as follows: B Version = 40°C to +85°C.
2
Guaranteed by design and characterization; not production tested.
3
See the
section.
Terminology
TIMING SPECIFICATIONS
V
DD
= 2.7 V to 3.6 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1
f
SCL
t
1
t
2
t
3
t
4
t
5
t
62
t
7
t
8
t
9
t
10
t
11
C
B
B Version
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns max
ns min
pF max
Description
SCL clock frequency
SCL cycle time
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
HD, STA
, start/repeated start condition hold time
t
SU, DAT
, data setup time
t
HD, DAT
, data hold time
t
SU, STA
, setup time for repeated start
t
SU, STO
, stop condition setup time
t
BUF
, bus free time between a stop condition and a start condition
t
R,
rise time of both SCL and SDA when receiving
May be CMOS driven
t
F
, fall time of SDA when receiving
t
F
, fall time of both SCL and SDA when transmitting
Capacitive load for each bus line
Limit at T
MIN
, T
MAX
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
300
20 + 0.1 C
B3
400
1
Guaranteed by design and characterization; not production tested.
2
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
INH MIN
of the SCL signal) to bridge the undefined region of the SCL falling edge.
3
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
are measured between 0.3 V
DD
and 0.7 V
DD
.
Timing Diagram
0
SDA
t
9
SCL
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
1
t
8
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 2. 2-Wire Serial Interface Timing Diagram
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