參數(shù)資料
型號： EVAL-AD5433EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 28/29頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD5433
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 1
位數(shù)： 10
采樣率（每秒）： 20.4M
數(shù)據(jù)接口： 并聯(lián)
設(shè)置時間： 35ns
DAC 型： 電流
工作溫度： -40°C ~ 125°C
已供物品： 板，CD
已用 IC / 零件： AD5433
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Data Sheet
AD5424/AD5433/AD5445
Rev. D | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03160-004
1
2
3
4
5
6
7
8
16
9
10
11
12
13
14
15
AD5424
(Not to Scale)
IOUT1
IOUT2
GND
DB7
DB6
DB5
DB4
DB3
RFB
VREF
VDD
R/W
CS
DB0 (LSB)
DB1
DB2
Figure 3. AD5424 Pin Configuration (TSSOP)
03160-
105
14
13
12
1
3
4
CS
15 R/W
NC
11 NC
GND
DB6
2
DB7
DB5
5
DB4
7
DB2
6
DB3
8
DB1
9
DB0
10
NC
19
I O
UT
1
20
I O
UT
2
18
R
FB
17
V
RE
F
16
V
DD
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
AD5424
TOP VIEW
(Not to Scale)
Figure 4. AD5424 Pin Configuration (LFCSP)
Table 4. AD5424 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1
19
IOUT1
DAC Current Output.
2
20
IOUT2
DAC Analog Ground. This pin should normally be tied to the analog ground of the system.
3
1
GND
Ground.
4 to 11
2 to 9
DB7 to DB0
Parallel Data Bits 7 to 0.
10 to 13
NC
No Internal Connection.
12
14
CS
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input
latch or to read data from the DAC register. Rising edge of CS loads data.
13
15
R/W
Read/Write. When low, use in conjunction with CS to load parallel data. When high, use with CS
to read back contents of DAC register.
14
16
VDD
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
15
17
VREF
DAC Reference Voltage Input Terminal.
16
18
RFB
DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to external
amplifier output.
Not applicable
EPAD
Exposed Pad. The exposed pad must be connected to AGND.
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