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| 型號： | EVAL-AD5433EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD5433 |
| 產(chǎn)品培訓(xùn)模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20.4M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 設(shè)置時間： | 35ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5433 |
| 相關(guān)產(chǎn)品： | AD5433YRUZ-ND - IC DAC 10BIT MULTIPLYING 20TSSOP AD5433YCPZ-ND - IC DAC 10BIT MULTIPLYING 20LFCSP AD5433YRUZ-REEL7-ND - IC DAC 10BIT MULTIPLYING 20TSSOP AD5433YRUZ-REEL-ND - IC DAC 10BIT MULTIPLYING 20TSSOP AD5433YRU-REEL-ND - IC DAC 10BIT MULTIPLYING 20TSSOP AD5433YRU-ND - IC DAC 10BIT MULTIPLYING 20TSSOP |
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AD5424/AD5433/AD5445
Data Sheet
Rev. D | Page 18 of 28
THEORY OF OPERATION
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit AD5424 is
value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If IOUT1 and IOUT2 are kept at the same
potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented
at VREF is always constant and nominally of resistance value R.
The DAC output (IOUT) is code-dependent, producing various
resistances and capacitances. External amplifier choice should
take into account the variation in impedance generated by the
DAC on the amplifiers inverting input node.
03160-048
VREF
RR
R
2R
S1
S2
S3
S8
2R
DAC DATA LATCHES
AND DRIVERS
RFBA
IOUT1
IOUT2
Figure 48. Simplified Ladder
Access is provided to the VREF, RFB, IOUT1, and IOUT2 terminals of
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for example,
to provide a unipolar output, 4-quadrant multiplication in bipolar
mode or in single-supply modes of operation. Note that a matching
switch is used in series with the internal RFB feedback resistor. If
users attempt to measure RFB, power must be applied to VDD to
achieve continuity.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 49.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
n
REF
OUT
D
V
2
where D is the fractional representation of the digital word loaded
to the DAC and n is the resolution of the DAC.
D = 0 to 255 (8-bit AD5424)
= 0 to 1023 (10-bit AD5433)
= 0 to 4095 (12-bit AD5445)
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages.
These DACs are designed to operate with either negative or positive
reference voltages. The VDD power pin is only used by the internal
digital logic to drive the DAC switches’ on and off states.
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 49 gives
a unipolar 0 V to –10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Table 7 shows the relationship between digital code and expected
output voltage for unipolar operation (AD5424, 8-bit device).
Table 7. Unipolar Code Table
Digital Input
Analog Output (V)
1111 1111
–VREF (255/256)
1000 0000
–VREF (128/256) = –VREF/2
0000 0001
VREF (1/256)
0000 0000
VREF (0/256) = 0
03160-049
VREF
VDD
R/W
R1
R2
IOUT1
IOUT2
CS
RFB
GND
C1
A1
AGND
DATA
INPUTS
VOUT =
0 TO –VREF
R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
NOTES:
1.
2.
AD5424/
AD5433/
AD5445
Figure 49. Unipolar Operation
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