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參數(shù)資料
| 型號： | EVAL-AD5425EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD5425 |
| 產(chǎn)品培訓模塊： | DAC Architectures |
| 標準包裝： | 1 |
| DAC 的數(shù)量： | 1 |
| 位數(shù)： | 8 |
| 采樣率（每秒）： | 2.47M |
| 數(shù)據(jù)接口： | 串行 |
| 設置時間： | 15ns |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 125°C |
| 已供物品： | 板，CD |
| 已用 IC / 零件： | AD5425 |
| 相關產(chǎn)品： | AD5425YRMZ-REEL7-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-REEL-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRMZ-ND - IC DAC 8BIT MULTIPLYING 10MSOP AD5425YRM-REEL7-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-REEL-ND - IC DAC 8BIT MULTIPLYING 10-MSOP AD5425YRM-ND - IC DAC MULTIPLYING 8BIT 10-MSOP |
Data Sheet
AD5425
Rev. C | Page 3 of 24
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: 40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE
Resolution
8
Bits
Relative Accuracy
±0.25
LSB
Differential Nonlinearity
±0.5
LSB
Guaranteed monotonic
Gain Error
±10
mV
Gain Error Temperature Coefficient
±5
ppm FSR/°C
Output Leakage Current
±10
nA
Data = 0x0000, T
A = 25°C, IOUT1
±20
nA
Data = 0x0000, T = 40°C to +125°C, I
OUT 1
REFERENCE INPUT1
Reference Input Range
±10
V
REF Input Resistance
8
10
12
kΩ
Input resistance TC = 50 ppm/°C
R
FB Resistance
8
10
12
kΩ
Input resistance TC = 50 ppm/°C
Input Capacitance
Code Zero Scale
3
6
pF
Code Full Scale
5
8
pF
DIGITAL INPUT/OUTPUT1
Input High Voltage, V
IH
1.7
V
Input Low Voltage, V
IL
0.6
V
Output High Voltage, V
OH
V
DD 1
V
DD = 4.5 V to 5 V, ISOURCE = 200 A
V
DD 0.5
V
DD = 2.5 V to 3.6 V, ISOURCE = 200 A
Output Low Voltage, V
OL
0.4
V
DD = 4.5 V to 5 V, ISINK = 200 A
0.4
V
DD = 2.5 V to 3.6 V, ISINK = 200 A
Input Leakage Current, I
IL
1
A
Input Capacitance
4
10
pF
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth
10
MHz
V
REF = ±3.5 V, DAC loaded all 1s
Output Voltage Settling Time
V
REF = ±3.5 V, RLOAD = 100 Ω, DAC latch
alternately loaded with 0s and 1s
Measured to ±1 mV
90
160
ns
Measured to ±4 mV
55
110
ns
Measured to ±16 mV
50
100
ns
Digital Delay
40
75
ns
Interface delay time
10% to 90% Settling Time
15
30
ns
Rise and fall time, V
REF = 10 V, RLOAD = 100 Ω
Digital-to-Analog Glitch Impulse
2
nV-s
1 LSB change around major carry V
REF = 0 V
Multiplying Feedthrough Error
DAC latch loaded with all 0s. V
REF = ±3.5 V
70
dB
1 MHz
48
dB
10 MHz
Output Capacitance
I
OUT1
12
17
pF
All 0s loaded
25
30
pF
All 1s loaded
I
OUT2
22
25
pF
All 0s loaded
10
12
pF
All 1s loaded
Digital Feedthrough
0.1
nV-s
Feedthrough to DAC output with SYNC high
and alternate loading of all 0s and all 1s
Analog THD
81
dB
V
REF = 3.5 V p-p; all 1s loaded, f = 1 kHz
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