參數(shù)資料
型號(hào)： EVAL-AD5391EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD5391
產(chǎn)品培訓(xùn)模塊： DAC Architectures
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 16
位數(shù)： 12
采樣率（每秒）： 167k
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 6µs
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板，CD
已用 IC / 零件： AD5391
相關(guān)產(chǎn)品： AD5391BSTZ-5-ND - IC DAC 12BIT 16CHAN 3V 52LQFP
AD5391BSTZ-3-ND - IC DAC 12BIT 16CHAN 3V 52LQFP
AD5391BCPZ-5-REEL7-ND - IC DAC 12BIT 16CHAN 5V 64LFCSP
AD5391BCPZ-5-REEL-ND - IC DAC 12BIT 16CHAN 5V 64-LFCSP
AD5391BCPZ-3-ND - IC DAC 12BIT I2C 16CH 3V 64LFCSP
AD5391BCPZ-5-ND - IC DAC 12BIT 16CH 5V 64-LFCSP
Data Sheet
AD5390/AD5391/AD5392
Rev. E | Page 23 of 44
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE
The AD5390/AD5391 are complete single-supply, 16-channel,
voltage output DACs offering a resolution of 14 bits and 12 bits,
respectively. The AD5392 is a complete single-supply, 8-channel,
voltage output DAC offering 14-bit resolution. All devices are
available in a 64-lead LFCSP and 52-lead LQFP, and feature
serial interfaces. This family includes an internal select-able
1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the
buffered reference inputs (alternatively, an external reference
can be used to drive these inputs). All channels have an on-chip
output amplifier with rail-to-rail output capable of driving a
5 kΩ load in parallel with a 200 pF capacitance.
The architecture of a single DAC channel consists of a 12-bit
and 14-bit resistor-string DAC followed by an output buffer
amplifier operating at a gain of 2. This resistor-string architecture
guarantees DAC monotonicity. The 12-bit and 14-bit binary
digital code loaded to the DAC register determines at what
node on the string the voltage is tapped off before being fed to
the output amplifier. Each channel on these devices contains
independent offset and gain control registers, allowing the user
to digitally trim offset and gain.
x1 INPUT
REG
m REG
c REG
x2
DAC
REG
14-BIT
DAC
INPUT
DATA
R
AVDD
VOUT
VREF
03773-
018
Figure 31. Single-Channel Architecture
These registers let the user calibrate out errors in the complete
signal chain including the DAC using the internal m and c
registers, which hold the correction factors. All channels are
double-buffered, allowing synchronous updating of all channels
using the LDAC pin. Figure 31 shows a block diagram of a
single channel on the AD5390/AD5391/AD5392.
The digital input transfer function for each DAC can be
represented as
(
)
(
)
(
)1
2
1
2
/
2
+
×
+
=
n
c
x
m
x
where:
x2 is the data-word loaded to the resistor-string DAC.
x1 is the 12-bit and 14-bit data-word written to the DAC input
register.
m is the 12-bit and 14-bit gain coefficient (default is all 0x3FFE
on the AD5390/AD5392 and 0xFFE on the AD5391). The LSB
of the gain coefficient is zero.
n = DAC resolution (n = 14 for the AD5390/AD5392 and
n = 12 for the AD5391).
c is the 12-bit and 14-bit offset coefficient (default is 0x2000 on
the AD5390/AD5392 and 0x800 on the AD5391).
The complete transfer function for these devices can be
represented as
n
x
VREF
VOUT
2
/
2
×
=
where:
x2 is the data-word loaded to the resistor-string DAC.
VREF is the reference voltage applied to the REFIN/REFOUT pin
on the DAC when an external reference is used (2.5 V for specified
performance on the AD539x-5 products and 1.25 V on the
AD539x-3 products).
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