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參數(shù)資料
| 型號： | EVAL-AD1974AZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD1974 |
| 標準包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| 輸入范圍： | 1.9 Vrms |
| 工作溫度： | -40°C ~ 125°C |
| 已用 IC / 零件： | AD1974 |
| 已供物品： | 板 |
AD1974
Data Sheet
Rev. D | Page 18 of 24
CONTROL REGISTERS
The global address for the AD1974 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address
R/W
Register Address
Data
Bit
23:17
16
15:8
7:0
Table 15. Register Addresses Description
Address
Function
0
PLL and Clock Control 0
1
PLL and Clock Control 1
2
AUXPORT Control 0
3
AUXPORT Control 1
4
AUXPORT Control 2
5
Reserved
6
Reserved
7
Reserved
8
Reserved
9
Reserved
10
Reserved
11
Reserved
12
Reserved
13
Reserved
14
ADC Control 0
15
ADC Control 1
16
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0
Bit
Value
Function
Description
0
Normal operation
PLL power-down
1
Power-down
2:1
00
INPUT 256 (×44.1 kHz or 48 kHz)
MCLKI/XI pin functionality (PLL active), master clock rate setting
01
INPUT 384 (×44.1 kHz or 48 kHz)
10
INPUT 512 (×44.1 kHz or 48 kHz)
11
INPUT 768 (×44.1 kHz or 48 kHz)
4:3
00
XTAL oscillator enabled
MCLKO/XO pin, master clock rate setting
01
256 × fS VCO output
10
512 × fS VCO output
11
Off
6:5
00
MCLKI/XI
PLL input
01
AUXLRCLK
10
ALRCLK
11
Reserved
7
0
Disable: ADC idle
Internal MCLK enable
1
Enable: ADC active
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