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參數(shù)資料
| 型號(hào)： | EVAL-AD1959EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | PLL/Multibit DAC |
| 中文描述： | 鎖相環(huán)/多比特DAC的 |
| 文件頁(yè)數(shù)： | 8/8頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | EVAL-AD1959EB |
REV. 0
–8–
C
AD1959
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
P
28-Lead Small Outline Package (SSOP)
(RS-28)
0.009 (0.229)
0.005 (0.127)
0.03 (0.762)
0.022 (0.558)
8
0
0.008 (0.203)
0.002 (0.050)
0.07 (1.79)
0.066 (1.67)
0.078 (1.98)
0.068 (1.73)
0.015 (0.38)
0.010 (0.25)
SEATING
PLANE
0.0256
(0.65)
BSC
0.311 (7.9)
0.301 (7.64)
0.212 (5.38)
0.205 (5.21)
28
15
14
1
0.407 (10.34)
0.397 (10.08)
PIN 1
Table I. DAC Control Register
Bit 11:10
Bit 9:8
Bit 7
Bit 6
Bit 5:4
Bit 3:2
Bit 1:0
Interpolation
Factor
Serial Data
Width
Serial Data
Format
De-Emphasis
Filter
SPI Register
Address
Output Phase
Soft Mute
00 = 8
×
*
01 = 4
×
10 = 2
×
11 = Not Allowed
00 = 24 Bits
*
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
0 = Noninverted
*
1 = Inverted
0 = No Mute
*
1 = Muted
00 = I
2
S
*
00 = Right Justified
10 = DSP
11 = Left Justified
00 = None
*
01 = 44.1 kHz
10 =32 kHz
11 = 48 kH
z
01
*
Default Setting.
Table II. DAC Volume Registers
B
it 15:2
Bit 1:0
Volume
SPI Register Address
14 Bits, Unsigned
14 Bits, Unsigned
00 = Left Volume
10 = Right Volume
Default is full volume.
Table III. PLL Control Register
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7:6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1:0
PLL2
Power-
Down
0 = On
*
1 = Power- 1 = Power-
Down
PLL1
Power-
Down
0 = On
*
XTAL
Power-
Down
0 = On
*
1 = Power-
Down
REF_Div2
Power-
Down
0 = No Div
*
1 = Div by 2
SPI
Register
Address
SCLK1
Select
0 =256
*
1 =384
SCLK2
Select
0 = 512
×
4.1 kHz
*
1 = 512
×
f
S
MCLK
Mode
0 = Output
*
11
1 = Input
f
S
00 = 48 kHz
*
01 = Not
Allowed
10 = 32 kHz
11 = 44.1 kHz
Double
0 = f
S
*
1 = 2
×
f
S
Down
*
Default Setting.
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