參數(shù)資料
型號： EPM9560ABI356-10
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 11.4 ns, PBGA356
封裝： BGA-356
文件頁數(shù)： 26/41頁
文件大?。?/td> 603K
代理商： EPM9560ABI356-10
32
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the MAX 9000 device recommended operating conditions, shown in Table 12 on
(2)
See Application Note 77 (Understanding MAX 9000 Timing) in this data book for more information on test conditions
tPD1 and tPD2 delays.
(3)
This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This
parameter applies for both global and array clocking as well as both macrocell and I/O cell registers.
(4)
Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB.
(5)
The tLPA parameter must be added to the tLOCAL parameter for macrocells running in low-power mode.
(6)
The tROW , tCOL, and tIOC delays are worst-case values for typical applications. Post-compilation timing simulation
or timing analysis is required to determine actual worst-case performance.
Power
Consumption
The supply power (P) versus frequency (
fMAX) for MAX 9000 devices can
be calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
The ICCINT value depends on the switching frequency and the application
logic.
The ICCINT value is calculated with the following equation:
ICCINT
= (A
× MC
TON) + [B × (MC DEV – MCTON)] + (C × MCUSED
× f
MAX × togLC)
Table 21. Interconnect Delays
Symbol
Parameter
Conditions
Speed Grade
Unit
-10
-15
-20
Min
Max
Min
Max
Min
Max
tLOCAL
LAB local array delay
0.5
ns
tROW
FastTrack row delay
0.9
1.4
2.0
ns
tCOL
FastTrack column delay
0.9
1.7
3.0
ns
tDIN_D
Dedicated input data delay
4.0
4.5
5.0
ns
tDIN_CLK
Dedicated input clock delay
2.7
3.5
4.0
ns
tDIN_CLR
Dedicated input clear delay
4.5
5.0
5.5
ns
tDIN_IOC
Dedicated input I/O register
clock delay
2.5
3.5
4.5
ns
tDIN_IO
Dedicated input I/O register
control delay
5.5
6.0
6.5
ns
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