參數(shù)資料
型號(hào): EPM7256B
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX7000B可編程邏輯系列器件)
文件頁(yè)數(shù): 23/125頁(yè)
文件大?。?/td> 1053K
代理商: EPM7256B
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Altera Corporation
23
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Two inverters implement the bus-hold circuitry in a loop that weakly
drives back to the I/ O pin at the end of programming.
Figure 10
shows a block diagram of the bus-hold circuit.
Figure 10. Bus-Hold Circuit
Power
Sequencing &
Hot-Socketing
Because MAX 7000B devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. The V
CCIO
and V
CCINT
power planes can be powered in any
order.
Signals can be driven into MAX 7000B devices before and during power
up without damaging the device. Additionally, MAX 7000B devices do
not drive out during power up. Once operating conditions are reached,
MAX 7000B devices operate as specified by the user.
Design Security
All MAX 7000B devices contain a programmable security bit that controls
access to the data programmed into the device. When this bit is
programmed, a design implemented in the device cannot be copied or
retrieved. This feature provides a high level of design security, because
programmed data within EEPROM cells is invisible. The security bit that
controls this function, as well as all other programmed data, is reset only
when the device is reprogrammed.
Generic Testing
MAX 7000B devices are fully functionally tested. Complete testing of each
programmable EEPROM bit and all internal logic elements ensures 100
%
programming yield. AC test measurements are taken under conditions
equivalent to those shown in
Figure 11
. Test patterns can be used and then
erased during early stages of the production flow.
I/O
RBH
Bus Hold Circuit
Drive to
VCCIO level
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