參數(shù)資料
型號(hào): EPM7064BFC100-5
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 3.5 ns, PBGA100
封裝: FBGA-100
文件頁數(shù): 50/66頁
文件大?。?/td> 962K
代理商: EPM7064BFC100-5
54
Altera Corporation
MAX 7000B Programmable Logic Device Data Sheet
Notes to tables:
(1)
These values are specified under the Recommended Operating Conditions in Table 15 on page 29. See Figure 14 for
more information on switching waveforms.
(2)
These values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.12 ns to the PIA timing value.
(3)
Measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
(4)
The tLPA parameter must be added to the tLAD, tLAC, tIC, tACL, tCPPW, tEN, and tSEXP parameters for macrocells
running in low-power mode.
Power
Consumption
Supply power (P) versus frequency (fMAX, in MHz) for MAX 7000B
devices is calculated with the following equation:
P = PINT + PIO = ICCINT × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices).
PCI
Input to PIA
0.0
ns
Input to global clock and clear
0.0
ns
Input to fast input register
0.0
ns
All outputs
0.0
ns
Table 32. EPM7512B Selectable I/O Standard Timing Adder Delays (Part 2 of 2)
Note (1)
I/O Standard
Parameter
Speed Grade
Unit
-5
-7
-10
Min
Max
Min
Max
Min
Max
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