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參數(shù)資料
| 型號(hào)： | EPM7064BFC100-5 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 3.5 ns, PBGA100 |
| 封裝： | FBGA-100 |
| 文件頁(yè)數(shù)： | 18/66頁(yè) |
| 文件大小： | 962K |
| 代理商： | EPM7064BFC100-5 |
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Altera Corporation
25
MAX 7000B Programmable Logic Device Data Sheet
Programmable Pull-Up Resistor
Each MAX 7000B device I/O pin provides an optional programmable
pull-up resistor during user mode. When this feature is enabled for an I/O
pin, the pull-up resistor (typically 50 k) weakly holds the output to
VCCIO level.
Bus Hold
Each MAX 7000B device I/O pin provides an optional bus-hold feature.
When this feature is enabled for an I/O pin, the bus-hold circuitry weakly
holds the signal at its last driven state. By holding the last driven state of
the pin until the next input signals is present, the bus-hold feature can
eliminate the need to add external pull-up or pull-down resistors to hold
a signal level when the bus is tri-stated. The bus-hold circuitry also pulls
undriven pins away from the input threshold voltage where noise can
cause unintended high-frequency switching. This feature can be selected
individually for each I/O pin. The bus-hold output will drive no higher
than VCCIO to prevent overdriving signals. The propagation delays
through the input and output buffers in MAX 7000B devices are not
affected by whether the bus-hold feature is enabled or disabled.
The bus-hold circuitry weakly pulls the signal level to the last driven state
through a resistor with a nominal resistance (RBH) of approximately
8.5 k. Table 12 gives specific sustaining current that will be driven
through this resistor and overdrive current that will identify the next
driven input level. This information is provided for each VCCIO voltage
level.
The bus-hold circuitry is active only during user operation. At power-up,
the bus-hold circuit initializes its initial hold value as VCC approaches the
recommended operation conditions. When transitioning from ISP to User
Mode with bus hold enabled, the bus-hold circuit captures the value
present on the pin at the end of programming.
Table 12. Bus Hold Parameters
Parameter
Conditions
VCCIO Level
Units
1.8 V
2.5 V
3.3 V
MinMax
Low sustaining current
VIN > VIL (max)
30
50
70
μA
High sustaining current
VIN < VIH (min)
–30
–50
–70
μA
Low overdrive current
0 V < VIN < VCCIO
200
300
500
μA
High overdrive current
0 V < VIN < VCCIO
–295
–435
–680
μA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM7064BFC100-7 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM7064BLC44-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-5 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BLC44-7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPM7064BTC100-3 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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