參數(shù)資料
型號(hào)： EPM7062B
廠商： Altera Corporation
英文描述： Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述： 可編程邏輯器件系列（MAX7000B可編程邏輯系列器件）
文件頁數(shù)： 5/125頁
文件大小： 1053K
代理商： EPM7062B
Altera Corporation
5
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 7000B devices provide programmable speed/ power optimization.
Speed-critical portions of a design can run at high speed/ full power,
while the remaining portions run at reduced speed/ low power. This
speed/ power optimization feature enables the designer to configure one
or more macrocells to operate at 50
%
or lower power while adding only a
nominal timing delay. MAX 7000B devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 7000B devices can be set for 3.3 V, 2.5 V, or 1.8 V and all input pins
are 3.3-V, 2.5-V, and 1.8-V tolerant, allowing MAX 7000B devices to be
used in mixed-voltage systems.
MAX 7000B devices are supported by the Quartus and MAX+PLUS II
development systems, which are integrated packages that offer
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The Quartus
software runs on Windows-based PCs, as well as Sun SPARCstation and
HP 9000 Series 700/ 800 workstations. The MAX+PLUS II software runs
on Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series
700/ 800, and IBM RISC System/ 6000 workstations.
f
For more information on development tools, see the
Logic Development System & Software Data Sheet
and the
Programmable Logic Development System & Software Data Sheet
.
Quartus Programmable
MAX+PLUS II
Functional
Description
The MAX 7000B architecture includes the following elements:
I
I
I
I
I
LABs
Macrocells
Expander product terms (shareable and parallel)
PIA
I/ O control blocks
The MAX 7000B architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/ O
pin.
Figure 1
shows the architecture of MAX 7000B devices.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7064 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family
EPM7064AE 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device
EPM7064AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7064AEFC100-4 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 64 Macro 68 IOs RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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