參數(shù)資料
型號(hào): EPM3256AQI208-6
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 6 ns, PQFP208
封裝: PLASTIC, QFP-208
文件頁(yè)數(shù): 14/43頁(yè)
文件大?。?/td> 716K
代理商: EPM3256AQI208-6
Altera Corporation
21
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
Signals can be driven into MAX 3000A devices before and during power
up without damaging the device. In addition, MAX 3000A devices do not
drive out during power up. Once operating conditions are reached,
MAX 3000A devices operate as specified by the user.
Timing Model
MAX 3000A device timing can be analyzed with the Quartus and
MAX+PLUS II software, with a variety of popular industry-standard
EDA simulators and timing analyzers, or with the timing model shown in
Figure 10. MAX 3000A devices have predictable internal delays that
enable the designer to determine the worst-case timing of any design. The
software provides timing simulation, point-to-point delay prediction, and
detailed timing analysis for device-wide performance evaluation.
Figure 10. MAX 3000A Timing Model
The timing characteristics of any signal path can be derived from the
timing model and parameters of a particular device. External timing
parameters, which represent pin-to-pin timing delays, can be calculated
as the sum of internal parameters. Figure 11 shows the timing relationship
between internal and external delay parameters.
Logic Array
Delay
t LAD
Output
Delay
t OD3
t OD2
t OD1
t XZ
Z
t X1
t ZX2
t ZX3
Input
Delay
t I N
Register
Delay
t SU
t H
t PRE
t CLR
t RD
t COMB
PIA
Delay
t PIA
Shared
Expander Delay
t SEXP
Register
Control Delay
t LAC
t IC
t EN
I/O
Delay
tIO
Global Control
Delay
t GLOB
Internal Output
Enable Delay
t IOE
Parallel
Expander Delay
t PEXP
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