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參數(shù)資料
| 型號(hào)： | EPF8636A |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE LOGIC DEVICES FAMILY |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數(shù)： | 5/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8636A |
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Altera Corporation
5
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 1
shows a block diagram of the FLEX 8000 architecture. Each
group of eight LEs is combined into an LAB; LABs are arranged into rows
and columns. The I/O pins are supported by I/O elements (IOEs) located
at the ends of rows and columns. Each IOE contains a bidirectional I/O
buffer and a flipflop that can be used as either an input or output register.
Figure 1. FLEX 8000 Device Block Diagram
Signal interconnections within FLEX 8000 devices and between device
pins are provided by the FastTrack Interconnect, a series of fast,
continuous channels that run the entire length and width of the device.
IOEs are located at the end of each row (horizontal) and column (vertical)
FastTrack Interconnect path.
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
I/O Element
(IOE)
Logic Array
Block (LAB)
Logic
Element (LE)
FastTrack
Interconnect
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| EPF8636AGC192-4 | 制造商:Altera Corporation 功能描述:Field-Programmable Gate Array, 504 Cell, 192 Pin, Ceramic, PGA |
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