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參數資料
| 型號： | EPF81188A |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE LOGIC DEVICES FAMILY |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數： | 32/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF81188A |
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32
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
Timing Model
The continuous, high-performance FastTrack Interconnect routing
structure ensures predictable performance and accurate simulation and
timing analysis. This predictable performance contrasts with that of
FPGAs, which use a segmented connection scheme and hence have
unpredictable performance. Timing simulation and delay prediction are
available with the MAX+PLUS II Simulator and Timing Analyzer, or with
industry-standard EDA tools. The Simulator offers both pre-synthesis
functional simulation to evaluate logic design accuracy and post-
synthesis timing simulation with 0.1-ns resolution. The Timing Analyzer
provides point-to-point timing delay information, setup and hold time
prediction, and device-wide performance analysis.
Tables 8
through
11
describe the FLEX 8000 timing parameters and their
symbols.
Table 8. FLEX 8000 Internal Timing Parameters
Note (1)
Symbol
Parameter
t
IOD
t
IOC
t
IOE
t
IOCO
t
IOCOMB
t
IOSU
t
IOH
t
IOCLR
t
IN
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
IOE register data delay
IOE register control signal delay
Output enable delay
IOE register clock-to-output delay
IOE combinatorial delay
IOE register setup time before clock; IOE register recovery time after asynchronous clear
IOE register hold time after clock
IOE register clear delay
Input pad and buffer delay
Output buffer and pad delay, slow slew rate = off, V
CCIO
= 5.0 V, C1 = 35 pF,
Note (2)
Output buffer and pad delay, slow slew rate = off, V
CCIO
= 3.3 V, C1 = 35 pF,
Note (2)
Output buffer and pad delay, slow slew rate = on, C1 = 35 pF,
Note (3)
Output buffer disable delay, C1 = 5 pF
Output buffer enable delay, slow slew rate = off, V
CCIO
= 5.0 V, C1 = 35 pF,
Note (2)
Output buffer enable delay, slow slew rate = off, V
CCIO
= 3.3 V, C1 = 35 pF,
Note (2)
Output buffer enable delay, slow slew rate = on, C1 = 35 pF,
Note (3)
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