參數(shù)資料
型號： EPF10K70RC240-3
廠商： Altera
文件頁數(shù)： 56/128頁
文件大?。?/td> 0K
描述： IC FLEX 10K FPGA 70K 240-RQFP
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
產(chǎn)品變化通告： Package Change 30/Jun/2010
標(biāo)準(zhǔn)包裝： 24
系列： FLEX-10K®
LAB/CLB數(shù)： 468
邏輯元件/單元數(shù)： 3744
RAM 位總計： 18432
輸入/輸出數(shù)： 189
門數(shù)： 118000
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-RQFP（32x32）
其它名稱： 544-2243
Altera Corporation
33
FLEX 10K Embedded Programmable Logic Device Family Data Sheet
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. The
internally generated signal can drive the global signal, providing the same
low-skew, low-delay characteristics for an internally generated signal as
for a signal driven by an input. This feature is ideal for internally
generated clear or clock signals with high fan-out. When a global signal is
driven by internal logic, the dedicated input pin that drives that global
signal cannot be used. The dedicated input pin should be driven to a
known logic state (such as ground) and not be allowed to float.
When the chip-wide output enable pin is held low, it will tri-state all pins
on the device. This option can be set in the Global Project Device Options
menu. Additionally, the registers in the IOE can be reset by holding the
chip-wide reset pin low.
Row-to-IOE Connections
When an IOE is used as an input signal, it can drive two separate row
channels. The signal is accessible by all LEs within that row. When an IOE
is used as an output, the signal is driven by a multiplexer that selects a
signal from the row channels. Up to eight IOEs connect to each side of
each row channel. See Figure 14.
Figure 14. FLEX 10K Row-to-IOE Connections
n
Each IOE is driven by an
m-to-1 multiplexer.
Each IOE can drive up to two
row channels.
IOE8
IOE1
m
Row FastTrack
Interconnect
n
The values for m and n are provided in Table 10.
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