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參數(shù)資料
| 型號： | EPF10K50SQC240-1N |
| 廠商： | Altera |
| 文件頁數(shù)： | 37/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FLEX 10KS FPGA 50K 240-PQFP |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 24 |
| 系列： | FLEX-10KE® |
| LAB/CLB數(shù)： | 360 |
| 邏輯元件/單元數(shù)： | 2880 |
| RAM 位總計： | 40960 |
| 輸入/輸出數(shù)： | 189 |
| 門數(shù)： | 199000 |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP |
| 供應商設備封裝： | 240-PQFP（32x32） |
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Altera Corporation
41
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during
device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if
tINCLKSTB is lower than 50 ps.
I/O
Configuration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting VCCIO to a different voltage than
VCCINT. Its effect can be simulated in the Altera software via the Global
Project Device Options
dialog box (Assign menu).
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
75
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
37.5
MHz
fCLKDEV
Input deviation from user
specification in the MAX+PLUS II
software
25,000
PPM
tINCLKSTB
Input clock stability (measured
between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or
ClockBoost to acquire lock
10
s
tJITTER
Jitter on ClockLock or ClockBoost-
generated clock
t INCLKSTB < 100
250
ps
t INCLKSTB < 50
200
ps
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
60
%
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EPF10K50SQC240-1X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC2402 | 制造商:ALTERA 功能描述:* |
| EPF10K50SQC240-2 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC240-2N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF10K50SQC240-2X | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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