參數(shù)資料
型號： EPF10K50SQC240-1N
廠商： Altera
文件頁數(shù)： 29/100頁
文件大?。?/td> 0K
描述： IC FLEX 10KS FPGA 50K 240-PQFP
產(chǎn)品培訓模塊： Three Reasons to Use FPGA's in Industrial Designs
標準包裝： 24
系列： FLEX-10KE®
LAB/CLB數(shù)： 360
邏輯元件/單元數(shù)： 2880
RAM 位總計： 40960
輸入/輸出數(shù)： 189
門數(shù)： 199000
電源電壓： 2.375 V ~ 2.625 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 240-BFQFP
供應商設備封裝： 240-PQFP（32x32）
34
Altera Corporation
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. An internally
generated signal can drive a global signal, providing the same low-skew,
low-delay characteristics as a signal driven by an input pin. An LE drives
the global signal by driving a row line that drives the peripheral bus,
which then drives the global signal. This feature is ideal for internally
generated clear or clock signals with high fan-out. However, internally
driven global signals offer no advantage over the general-purpose
interconnect for routing data signals. The dedicated input pin should be
driven to a known logic state (such as ground) and not be allowed to float.
The chip-wide output enable pin is an active-high pin (DEV_OE) that can
be used to tri-state all pins on the device. This option can be set in the
Altera software. On EPF10K50E and EPF10K200E devices, the built-in I/O
pin pull-up resistors (which are active during configuration) are active
when the chip-wide output enable pin is asserted. The registers in the IOE
can also be reset by the chip-wide reset pin.
Table 9. Peripheral Bus Sources for EPF10K100E, EPF10K130E, EPF10K200E & EPF10K200S Devices
Peripheral
Control Signal
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K200S
OE0
Row A
Row C
Row G
OE1
Row C
Row E
Row I
OE2
Row E
Row G
Row K
OE3
Row L
Row N
Row R
OE4
Row I
Row K
Row O
OE5
Row K
Row M
Row Q
CLKENA0/CLK0/GLOBAL0
Row F
Row H
Row L
CLKENA1/OE6/GLOBAL1
Row D
Row F
Row J
CLKENA2/CLR0
Row B
Row D
Row H
CLKENA3/OE7/GLOBAL2
Row H
Row J
Row N
CLKENA4/CLR1
Row J
Row L
Row P
CLKENA5/CLK1/GLOBAL3
Row G
Row I
Row M
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相關代理商/技術參數(shù)
參數(shù)描述
EPF10K50SQC240-1X 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50SQC2402 制造商:ALTERA 功能描述:*
EPF10K50SQC240-2 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50SQC240-2N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K50SQC240-2X 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 10K 360 LABs 189 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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