參數(shù)資料
型號: EPF10K100BFI256-2DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 74/120頁
文件大?。?/td> 1901K
代理商: EPF10K100BFI256-2DX
Altera Corporation
57
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Table 26. EAB Timing Microparameters
Symbol
Parameter
Conditions
tEABDATA1
Data or address delay to EAB for combinatorial input
tEABDATA2
Data or address delay to EAB for registered input
tEABWE1
Write enable delay to EAB for combinatorial input
tEABWE2
Write enable delay to EAB for registered input
tEABRE1
Read enable delay to EAB for combinatorial input
tEABRE2
Read enable delay to EAB for registered input
tEABCLK
EAB register clock delay
tEABCO
EAB register clock-to-output delay
tEABBYPASS
Bypass register delay
tEABSU
EAB register setup time before clock
tEABH
EAB register hold time after clock
tEABCLR
EAB register asynchronous clear time to output delay
tEABCH
Clock high time
tEABCL
Clock low time
tAA
Address access delay (including the read enable to output delay)
tWP
Write pulse width
tRP
Read pulse width
tWDSU
Data setup time before falling edge of write pulse
tWDH
Data hold time after falling edge of write pulse
tWASU
Address setup time before rising edge of write pulse
tWAH
Address hold time after falling edge of write pulse
tRASU
Address setup time with respect to the falling edge of the read enable
tRAH
Address hold time with respect to the falling edge of the read enable
tWO
Write enable to data output valid delay
tDD
Data-in to data-out valid delay
tEABOUT
Data-out delay
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