參數(shù)資料
型號: EPF10K100BFC256-1DX
英文描述: ASIC
中文描述: 專用集成電路
文件頁數(shù): 49/120頁
文件大?。?/td> 1901K
代理商: EPF10K100BFC256-1DX
34
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3 in Tables 8 and 9. An internally
generated signal can drive a global signal, providing the same low-skew,
low-delay characteristics as a signal driven by an input pin. An LE drives
the global signal by driving a row line that drives the peripheral bus,
which then drives the global signal. This feature is ideal for internally
generated clear or clock signals with high fan-out. However, internally
driven global signals offer no advantage over the general-purpose
interconnect for routing data signals.
The chip-wide output enable pin is an active-low pin that can be used to
tri-state all pins on the device. This option can be set in the
MAX+PLUS II software. On EPF10K50E and EPF10K200E devices, the
built-in I/O pin pull-up resistors (which are active during configuration)
are active when the chip-wide output enable pin is asserted. The registers
in the IOE can also be reset by the chip-wide reset pin.
Table 9. Peripheral Bus Sources for EPF10K100B, EPF10K100E, EPF10K130E, EPF10K200E &
EPF10K200S Devices
Peripheral
Control Signal
EPF10K100B
EPF10K100E
EPF10K130E
EPF10K200E
EPF10K200S
OE0
Row A
Row C
Row G
OE1
Row C
Row E
Row I
OE2
Row E
Row G
Row K
OE3
Row L
Row N
Row R
OE4
Row I
Row K
Row O
OE5
Row K
Row M
Row Q
CLKENA0/CLK0/GLOBAL0
Row F
Row H
Row L
CLKENA1/OE6/GLOBAL1
Row D
Row F
Row J
CLKENA2/CLR0
Row B
Row D
Row H
CLKENA3/OE7/GLOBAL2
Row H
Row J
Row N
CLKENA4/CLR1
Row J
Row L
Row P
CLKENA5/CLK1/GLOBAL3
Row G
Row I
Row M
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