參數(shù)資料
型號(hào)： EPC1064V
廠商： Altera Corporation
英文描述： Configuration Devices for ACEX, APEX, FLEX & Mercury Devices
中文描述： 配置器件ACEX，頂點(diǎn)，柔性
文件頁數(shù)： 21/28頁
文件大?。?/td> 380K
代理商： EPC1064V
Altera Corporation
21
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
The EPC2 configuration device can be programmed in-system through its
industry-standard 4-pin JTAG interface. ISP capability in the EPC2
provides ease in prototyping and updating ACEX, APEX, FLEX, and
Mercury device functionality. The EPC2 configuration device can be
programmed in-system via test equipment using SVF Files, Jam STAPL
Files (
.jam
), or Jam STAPL Byte-Code Files (
.jbc
), embedded processors
using the Jam programming and test language, and the MAX+PLUS II
software via the MasterBlaster, ByteBlasterMV, or BitBlaster download
cables. When programming multiple EPC2 devices in a JTAG chain, the
Quartus and MAX+PLUS II software and other programming methods
employ concurrent programming to simultaneously program multiple
devices and reduce programming time. EPC2 devices can be programmed
and erased up to 100 times.
After programming an EPC2 device in-system, ACEX, APEX, FLEX, or
Mercury device configuration can be initiated by including the EPC2
JTAG configuration instruction. See
Table8 on page21
.
f
For more information on programming and configuration support, see the
following documents:
I
I
I
I
I
I
Programming Hardware Manufacturers
MasterBlaster Serial/USB Communications Cable Data Sheet
ByteBlasterMV Parallel Port Download Cable Data Sheet
ByteBlaster Parallel Port Download Cable Data Sheet
BitBlaster Serial Download Cable Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Testing
The EPC2 provides JTAG BST circuitry that complies with the IEEE Std.
1149.1-1990 specification. JTAG boundary-scan testing can be performed
before or after configuration, but not during configuration. The EPC2
device supports the JTAG instructions shown in
Table8
.
The ISP circuitry in EPC2 devices is compatible with tools that support the
IEEE Std. 1532. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Table 8. EPC2 JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD
Allows a snapshot of a signal at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern output at the device pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing results at the input pins.
EXTEST
相關(guān)PDF資料
PDF描述
EPC1213 Configuration Devices for ACEX, APEX, FLEX & Mercury Devices
EPC1441 Configuration Devices for ACEX, APEX, FLEX & Mercury Devices
EPC4xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPC1064VLC20 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPC1064VLC-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM
EPC1064VLI-20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM
EPC1064VPC8 制造商:Rochester Electronics LLC 功能描述:- Bulk
EPC1064VPC-8 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM
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