參數(shù)資料
型號(hào)： EP9315-IB
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Metal Strip Resistor; Series:WSL; Resistance:0.003ohm; Resistance Tolerance:+/- 1 %; Power Rating:0.25W; Temperature Coefficient:+/-150 ppm; Package/Case:1206; Terminal Type:PCB Surface Mount; Leaded Process Compatible:Yes
中文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 27 X 27 MM, PLASTIC, MO-151BAL-2, BGA-352
文件頁(yè)數(shù)： 60/64頁(yè)
文件大小： 1031K
代理商： EP9315-IB
60
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
EP9315
Enhanced Universal Platform SOC Processor
The following section focuses on the EP9315 pin signals
from two viewpoints - the pin usage and pad
characteristics, and the pin multiplexing usage. The first
table (
Table S
) is a summary of all the EP9315 pin
signals. The second table (
Table T
) illustrates the pin
signal multiplexing and configuration options.
Table S
is a summary of the EP9315 pin signals, which
illustrates the pad type and pad pull type (if any). The
symbols used in the table are defined as follows. (Note: A
blank box means Not Applicable (NA) or, for Pull Type,
No Pull (NP).)
Under the Pad Type column:
See the text description for additional information about
bi-directional pins.
A - Analog pad
P - Power pad
G - Ground pad
I - Pin is an input only
I/O - Pin is input/output
4mA - Pin is a 4 mA output driver
8mA - Pin is an 8 mA output driver
12mA - Pin is an 12 mA output driver
Under the Pull Type Column:
PU - Resistor is a pull up to the RVDD supply
PD - Resistor is a pull down to the RGND supply
.
Table S. Pin Descriptions
Pin Name
Block
Pad
Type
Pull
Type
Description
TCK
JTAG
I
PD
JTAG clock in
TDI
JTAG
I
PD
JTAG data in
TDO
JTAG
4ma
JTAG data out
TMS
JTAG
I
PD
JTAG test mode select
TRSTn
JTAG
I
PD
JTAG reset
BOOT[1:0]
System
I
PD
Boot mode select in
XTALI
PLL
A
Main oscillator input
XTALO
PLL
A
Main oscillator output
VDD_PLL
PLL
P
Main oscillator power, 1.8V
GND_PLL
PLL
G
Main oscillator ground
RTCXTALI
RTC
A
RTC oscillator input
RTCXTALO
RTC
A
RTC oscillator output
WRn
EBUS
4ma
SRAM Write strobe out
RDn
EBUS
4ma
SRAM Read / OE strobe out
WAITn
EBUS
I
PU
SRAM Wait in
AD[25:0]
EBUS
8ma
Shared Address bus out
DA[31:0]
EBUS
8ma
PU
Shared Data bus in/out
CSn[3:0]
EBUS
4ma
PU
Chip select out
CSn[7:6]
EBUS
4ma
PU
Chip select out
DQMn[3:0]
EBUS
8ma
Shared data mask out
SDCLK
SDRAM
8ma
SDRAM clock out
SDCLKEN
SDRAM
8ma
SDRAM clock enable out
SDCSn[3:0]
SDRAM
4ma
SDRAM chip selects out
RASn
SDRAM
8ma
SDRAM RAS out
CASn
SDRAM
8ma
SDRAM CAS out
SDWEn
SDRAM
8ma
SDRAM write enable out
P[17:0]
Raster
4ma
PU
Pixel data bus out
SPCLK
Raster
12ma
PU
Pixel clock in/out
HSYNC
Raster
8ma
PU
Horizontal synchronization / line pulse out
V_CSYNC
Raster
8ma
PU
Vertical or composite synchronization / frame
pulse out
BLANK
Raster
8ma
PU
Composite blanking signal out
BRIGHT
Raster
4ma
PWM brightness control out
PWMOUT
PWM
8ma
Pulse width modulator output
Xp, Xm
ADC
A
Touchscreen ADC X axis
Yp, Ym
ADC
A
Touchscreen ADC Y axis
sXp, sXm
ADC
A
Touchscreen ADC X axis feedback
sYp, sYm
ADC
A
Touchscreen ADC Y axis feedback
VDD_ADC
ADC
P
Touchscreen ADC power, 3.3V
GND_ADC
ADC
G
Touchscreen ADC ground
COL[7:0]
Key
8ma
PU
Key matrix column inputs
ROW[7:0]
Key
8ma
PU
Key matrix row outputs
USBp[2:0]
USB
A
USB positive signals
USBm[2:0]
USB
A
USB negative signals
TXD0
UART1
4ma
Transmit out
RXD0
UART1
I
PU
Receive in
CTSn
UART1
I
PU
Clear to send / transmit enable
DSRn
UART1
I
PU
Data set ready / Data Carrier Detect
DTRn
UART1
4ma
Data Terminal Ready output
RTSn
UART1
4ma
Ready to send
TXD1
UART2
4ma
Transmit / IrDA output
RXD1
UART2
I
PU
Receive / IrDA input
TXD2
UART3
4ma
Transmit
RXD2
UART3
I
PU
Receive
MDC
EMAC
4ma
Management data clock
Table S. Pin Descriptions
(Continued)
Pin Name
Block
Pad
Type
Pull
Type
Description
相關(guān)PDF資料
PDF描述
EP9315-IBZ Enhanced Universal Platform System-on-Chip Processor
EP9315 Enhanced Universal Platform System-on-Chip Processor
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EP9315-CBZ Enhanced Universal Platform System-on-Chip Processor
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