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| 型號： | EP9315-EBZ |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Enhanced Universal Platform System-on-Chip Processor |
| 中文描述： | 增強型通用平臺上系統(tǒng)芯片處理器 |
| 文件頁數(shù)： | 9/64頁 |
| 文件大小： | 1031K |
| 代理商： | EP9315-EBZ |
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DS638PP4
Copyright 2005 Cirrus Logic (All Rights Reserved)
9
EP9315
Enhanced Universal Platform SOC Processor
Universal Asynchronous
Receiver/Transmitters (UARTs)
Three 16550-compatible UARTs are supplied. Two
provide asynchronous HDLC (High-level Data Link
Control) protocol support for full-duplex transmit and
receive. The HDLC receiver handles framing, address
matching, CRC checking, control-octet transparency, and
optionally passes the CRC to the host at the end of the
packet. The HDLC transmitter handles framing, CRC
generation, and control-octet transparency. The host
must
assemble
the
frame
transmission. The HDLC receiver and transmitter use the
UART FIFOs to buffer the data streams. A third IrDA
-
compatible UART is also supplied.
in
memory
before
UART1 supports modem bit rates up to 115.2 Kbps,
supports HDLC and includes a 16-byte FIFO for
receive and a 16-byte FIFO for transmit. Interrupts are
generated on Rx, Tx, and modem status change.
UART2 contains an IrDA encoder operating at either
the slow (up to 115 Kbps), medium (0.576 or 1.152
Mbps), or fast (4 Mbps) IR data rates. It also has a 16-
byte FIFO for receive and a 16-byte FIFO for transmit.
UART3 supports HDLC and includes a 16-byte FIFO
for receive and a 16-byte FIFO for transmit. Interrupts
are generated on Rx and Tx.
Triple Port USB Host
The USB Open Host Controller Interface (Open HCI)
provides full speed serial communications ports at a
baud rate of 12 Mbits/sec. Up to 127 USB devices
(printer, mouse, camera, keyboard, etc.) and USB hubs
can be connected to the USB host in the USB “tiered-
start” topology.
This includes the following features:
Compliance with the USB 2.0 specification
Compliance with the Open HCI Rev 1.0 specification
Supports both low speed (1.5 Mbps) and full speed
(12 Mbps) USB device connections
Root HUB integrated with 3 downstream USB ports
Transceiver buffers integrated, over-current protection
on ports
Supports power management
Operates as a master on the bus
The Open HCI host controller initializes the master DMA
transfer with the AHB bus:
Fetches endpoint descriptors and transfer descriptors
Accesses endpoint data from system memory
Accesses the HC communication area
Writes status and retire transfer descriptor
Two-wire Interface
The two-wire interface provides communication and
control for synchronous-serial-driven devices.
Table I. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Pin Mnemonic
Pin Name - Description
TXD0
UART1 Transmit
RXD0
UART1 Receive
CTSn
UART1 Clear To Send /
Transmit Enable
DSRn / DCDn
UART1 Data Set Ready /
Data Carrier Detect
DTRn
UART1 Data Terminal Ready
RTSn
UART1 Ready To Send
EGPIO[0] / RI
UART1 Ring Indicator
TXD1 / SIROUT
UART2 Transmit /
IrDA Output
RXD1 / SIRIN
UART2 Receive / IrDA Input
TXD2
UART3 Transmit
RXD2
UART3 Receive
EGPIO[3] / TENn
HDLC3 Transmit Enable
Table J. Triple Port USB Host Pin Assignments
Pin Mnemonic
Pin Name - Description
USBp[2:0]
USB Positive signals
USBm[2:0]
USB Negative Signals
Table K. Two-Wire Port with EEPROM Support Pin Assignments
Pin Mnemonic
Pin Name - Description
Alternative
Usage
EECLK
Two-Wire Interface Clock
General
Purpose I/O
EEDATA
Two-Wire Interface Data
General
Purpose I/O
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