參數(shù)資料
型號(hào)： EP9315-CB
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Enhanced Universal Platform System-on-Chip Processor
中文描述： 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352
封裝： 27 X 27 MM, PLASTIC, MO-151BAL-2, BGA-352
文件頁(yè)數(shù)： 36/64頁(yè)
文件大小： 1031K
代理商： EP9315-CB
36
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS638PP4
EP9315
Enhanced Universal Platform SOC Processor
Ultra DMA Data Transfer
Figure 21
through
Figure 30
define the timings associated with all phases of Ultra DMA bursts. The following table
contains the values for the timings for each of the Ultra DMA modes.
Note:
1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies.
2. The test load for t
DVS
and t
DVH
shall be a lumped capacitor load with no cable or receivers. Timing for t
DVS
and t
DVH
shall be
met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value.
3. t
UI
, t
MLI
and t
LI
indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the
other to respond with a signal before proceeding. t
UI
is an unlimited interlock that has no maximum time value. t
MLI
is a limited
time-out that has a defined minimum. t
LI
is a limited time-out that has a defined maximum.
4. t
ZIORDY
may be greater than t
ENV
since the device has a pull up on IORDYn giving it a known state when released.
5. All IDE timing is based upon HCLK = 100 MHz.
Timing reference levels = 1.5 V
Parameter
Symbol
Mode 0
(in ns)
min
Mode 1
(in ns)
min
Mode 2
(in ns)
min
Mode 3
(in ns)
min
max
max
max
max
Cycle time allowing for asymmetry and clock variations
(from DSTROBE edge to DSTROBE edge)
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of DSTROBE)
Cycle time allowing for asymmetry and clock variations
(from HSTROBE edge to HSTROBE edge)
Two-cycle time allowing for clock variations (from rising edge to next
rising edge or from falling edge to next falling edge of HSTROBE)
Data setup time at recipient (Read)
t
CYCRD
112
-
73
-
54
-
39
-
t
2CYCRD
230
-
154
-
115
-
86
-
t
CYCWR
230
-
170
-
130
-
100
-
t
2CYCWR
460
-
340
-
260
-
200
-
t
DS
t
DH
15
-
10
-
7
-
7
-
Data hold time at recipient (Read)
Data valid setup time at sender (Write)
(from data valid until STROBE edge)
Data valid hold time at sender (Write)
(from STROBE edge until data may become invalid)
First STROBE time (for device to first negate DSTROBE from STOP
during a data in burst)
Limited interlock time
8
-
8
-
8
-
8
-
(Note 2)
t
DVS
70
-
48
-
30
-
20
-
(Note 2)
t
DVH
6
-
6
-
6
-
6
-
t
FS
0
230
0
200
0
170
0
130
(Note 3)
t
LI
t
MLI
t
UI
0
150
0
150
0
150
0
100
Interlock time with minimum
(Note 3)
20
-
20
-
20
-
20
-
Unlimited interlock time
Maximum time allowed for output drivers to release
(from asserted or negated)
Minimum delay time required for output
(Note 3)
0
-
0
-
0
-
0
-
t
AZ
-
10
-
10
-
10
-
10
t
ZAH
t
ZAD
20
-
20
-
20
-
20
-
Drivers to assert or negate (from released)
Envelope time (from DMACKn to STOP and HDMARDYn during data in
burst initiation and from DMACKn to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long
after negation of DMARDYn)
Ready-to-pause time
(that recipient shall wait to pause after negating DMARDYn)
Maximum time before releasing IORDY
0
-
0
-
0
-
0
-
t
ENV
20
70
20
70
20
70
20
55
t
RFS
-
75
-
70
-
60
-
60
t
RP
160
-
125
-
100
-
100
-
t
IORDYZ
t
ZIORDY
t
ACK
-
20
-
20
-
20
-
20
Minimum time before driving STROBE
(Note 4)
0
-
0
-
0
-
0
-
Setup and hold times for DMACKn (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP
(when sender terminates a burst)
20
-
20
-
20
-
20
-
t
SS
50
-
50
-
50
-
50
-
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參數(shù)描述
EP9315CB/E0 制造商:Cirrus Logic 功能描述:
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EP9315-EBZ 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Enhanced Universal Platform System-on-Chip Processor
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