參數(shù)資料
型號(hào)： EP9312-IB
廠商： CIRRUS LOGIC INC
元件分類： 微控制器/微處理器
英文描述： Universal Platform System-on-chip Processor
中文描述： 32-BIT, 184 MHz, RISC PROCESSOR, PBGA352
封裝： 27 X 27 MM, PLASTIC, BGA-352
文件頁(yè)數(shù)： 51/62頁(yè)
文件大?。?/td> 884K
代理商： EP9312-IB
DS515PP7
Copyright 2005 Cirrus Logic (All Rights Reserved)
51
EP9312
Universal Platform SOC Processor
ADC
Note:
ADIV refers to bit 16 in the KeyTchClkDiv register.
ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4.
ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16.
Using the ADC:
This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a
conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register
contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay
between each successful conversion and the issue of the next conversion command, or else the returned value of
successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the
same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion.
Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.
The following is a recommended procedure for safely polling the ADC from software:
1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.
Parameter
Comment
Value
Units
Resolution
No missing codes
Range of 0 to 3.3 V
50K counts (approximate)
Integral non-linearity
0.01%
Offset error
±15
mV
Full scale error
0.2%
Maximum sample rate
ADIV = 0
ADIV = 1
3750
925
Samples per second
Samples per second
Channel switch settling time
ADIV = 0
ADIV = 1
500
2
μ
s
ms
Noise (RMS) - typical
120
μ
V
Figure 36. ADC Transfer Function
0
Vref/2
Vref
0000
FFFF
61A8
9E58
A/D Converter Transfer Function
(approximately ±25,000 counts)
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