參數(shù)資料
型號: EP9312-IB
廠商: CIRRUS LOGIC INC
元件分類: 微控制器/微處理器
英文描述: Universal Platform System-on-chip Processor
中文描述: 32-BIT, 184 MHz, RISC PROCESSOR, PBGA352
封裝: 27 X 27 MM, PLASTIC, BGA-352
文件頁數(shù): 15/62頁
文件大?。?/td> 884K
代理商: EP9312-IB
DS515PP7
Copyright 2005 Cirrus Logic (All Rights Reserved)
15
EP9312
Universal Platform SOC Processor
Memory Interface
SDRAM Load Mode Register Cycle
Figure 2
through
Figure 5
define the timings associated with all phases of the SDRAM. The following table contains the
values for the timings of each of the SDRAM modes.
Parameter
Symbol
Min
Typ
Max
Unit
SDCLK high time
t
clk_high
-
(t
HCLK
) / 2
-
ns
SDCLK low time
t
clk_low
-
(t
HCLK
) / 2
-
ns
SDCLK rise/fall time
t
clkrf
-
2
4
ns
Signal delay from SDCLK rising edge time
t
d
-
-
8
ns
Signal hold from SDCLK rising edge time
t
h
1
-
-
ns
DQMn delay from SDCLK rising edge time
t
DQd
-
-
8
ns
DQMn hold from SDCLK rising edge time
t
DQh
1
-
-
ns
DA valid setup to SDCLK rising edge time
t
DAs
2
-
-
ns
DA valid hold from SDCLK rising edge time
t
DAh
3
-
-
ns
Figure 2. SDRAM Load Mode Register Cycle Timing Measurement
SDCLK
SDCSn
RASn
CASn
SDWEn
DQMn
AD
DA
OP-Code
t
clk_high
t
clk_low
t
clkrf
t
d
t
h
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